• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.71-78
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• 2019

As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.61-66
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• 2018

This research scrutinizes the self-annealing characteristics of copper used to metal interconnection for application of DRAM fabrication process. As the time goes after the copper deposited, the grain of copper is growing. It is called self-annealing. We use the electroplating method for copper deposition and estimate two kinds of electroplating chemicals having different organic additives. As the time of self-annealing is elapsed, sheet resistance decreases with logarithmic dependence of time and is finally saturated. The improvement of sheet resistance is approximately 20%. The saturation time of experimental sample is shorter than that of reference sample. We can find that self-annealing is highly efficient in grain growth of copper through the measurement of TEM analysis. The structure of copper grain is similar to the bamboo type useful for current flow. The results of thermal excursion characteristics show that the reliability of self-annealed sample is better than that of sample annealed at higher temperature. The self-annealed sample is not contained in hillock. The self-annealed samples grow until $2{\mu}m$ and develop in [100] direction more favorable for reliability.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.784-787
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• 2002

We prepared the PLT(28) thin film by using sol-gel method and investigated the structure and electrical properties of the film. With the XRD and AFM analyses, it is found that PLT(28) thin film annealed at 6sot has a complete perovskite structure and its surface roughness is about 22$\AA$. We prepared PLT(28) thin film on the Pt/TiO$_{x}$SiO$_2$/Si substrate, in which the specimen has a planar capacitor structure, and analyzed the electrical properties of PLT(28) thin film. In result, PLT(28) thin film has a paraelectric phase and its dielectric constant and loss tangent at 10kHz are 761 and 0.024, respectively. Also, the storage charge density and leakage current density of PLT(28) thin film at W are 134fC/$\mu$m2 and 1.01 $\mu$A/cm2, respectively. As a result of this, we concluded that the PLT(28) thin film is a promising material to be used as a capacitor dielectrics for next generation DRAM.M.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.5
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• pp.417-422
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• 2001

The needs of new materials that substitute Si Oxide capacitor layer in high density DRAM increase. So in this paper, we choose the slim region 14/50/50 PLZT composition and fabricated thin films by PLD and estimated the characteristics for DRAM application. 14/50/50 PLZT thin films have crystallized into perovskite structure in the $600^{\circ}C$ deposition temperature and 200 mTorr Oxygen pressure. In this condition, PLZT thin films had 985 dielectric constant, storage charge density 8.17 $\mu$C/$\textrm{cm}^2$ and charging time 0.20ns. Leakage Current density was less than 10$^{-10}$ A/$\textrm{cm}^2$ until 5V bias voltage.

• ETRI Journal
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• v.30 no.4
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• pp.612-614
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• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.278-281
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• 1999

PLZT thin films on Pt/Ti/SiO$_2$/Si substrate were fabricated with different Thickness by pulsed laser deposition. 14/50/50 PLZT thin film showed a maximum dielectric constant value of $\varepsilon$$_{t}$=985 at 5000$\AA$, and $\varepsilon$$_{t}$=668 at 2000A. P-EI hysteresis loop of 14/50/50 PLZT thin film was slim ferroelectric. Leakage current density of 14/50/70 PLZT thin film was 10$^{-8}$ A/$\textrm{cm}^2$ at 2000$\AA$.EX>.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.79-86
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• 2019

For decades, in-memory data structures have been designed for DRAM-based main memory that provides symmetric read/write performances and has no limited write endurance. However, such data structures provide sub-optimal performance for NVM as it has different characteristics to DRAM. With this motivation, we rethink a conventional red-black tree in terms of its efficacy under NVM settings. The original red-black tree constantly rebalances sub-trees so as to export fast access time over dataset, but it inevitably increases the write traffic, adversely affecting the performance for NVM with a long write latency and limited endurance. To resolve this problem, we present a variant of the red-black tree called a hierarchical balanced binary search tree. The proposed structure maintains multiple keys in a single node so as to amortize the rebalancing cost. The performance study reveals that the proposed hierarchical binary search tree effectively reduces the write traffic by effectively reaping the high capacity of NVM.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.3
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• pp.344-349
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• 2006

The low-temperature processing is very important for fabrication of the very large scale ($60{\sim}70nm$) semiconductor devices since the submicron transistors are sensitive to the thermal budget. Hence, in this work, we propose a noble low-temperature LPCVD (Low-Pressure Chemical Vapor Deposition) process for the $SiO_2$ film and evaluate the electrical reliability of the LTO (Low-Temperature Oxide) by making the capacitors with ONO (Oxide/Nitride/Oxide) structure. The leak current of the LTO was similar to that of the high-temperature wet oxide until the electric field was lower than 5 MV/cm. However, when the electric field was higher, the LTO showed much better characteristics.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.2
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• pp.137-143
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• 2015

During the past 30 years, DRAM has been used for the reasons of economic efficiency of the production. Recently, PRAM has been emerged to overcome the shortcomings of DRAM. In this paper, we propose a technique that can reduce energy consumption by use of a narrow values to the write operation of PRAM. For this purpose, we describe the data compression method using a narrow value and the architecture of PRAM, We also experiment under the Simplescalar 3.0e simulator and SPEC CPU2000 benchmark environments. According to the experiments, the data hit rate of PRAM was increased by 39.4% to 67.7% and energy consumption was reduced by 9.2%. In order to use the proposed technique, it requires 3.12% of space overhead per word, and some additional hardware modules.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.33 no.2
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• pp.16-41
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• 2015