• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1128-1135
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• 2001

In this paper, a new HSG-Si formation technology, "seeding method', which employs Si$_2$H$_{6}$-molecule irradiation and annealing, was applied for realizing 64Mbit DRAMs. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous-doped amorphous-Si electrode. The new HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors. In this technique, optimum process conditions of the phosphorous concentration, storage polysilicon deposition temperature and thickness of hemispherical grain silicon are in the range of 3.0-4.0E19atoms/㎤, 53$0^{\circ}C$ and 400$\AA$, respectively. In the 64M bit DRAM capacitor using optimum process conditions, limit thickness of dielectric nitride is about 65$\AA$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.2
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• pp.133-137
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• 1998

$(Pb_{0.72}La_{0.28})Ti_{0.93}O_3(PLT(28))$ thin films were fabricated by pulsed laser deposition. PLT films deposited on $Pt/Ti/SiO_2/Si$ at $600^{\circ}C$ had a preferred orientation in (111) plane and at $550^{\circ}C$ had a (100) preferred orientation. We found that (111) preferred oriented films had well grown normal to substrate surface. This PLT(28) thin films of $1{\mu}m$ thickness had dielectric properties of ${\varepsilon}_r$=1300, dielectric $loss{\fallingdotseq}0.03 $. and had charge storage density of 10 [${\mu}C/cm^2$] and leakage current density of less than $10^{-6}[A/cm^2]$ at 100[kV/cm]. These results indicated that the PLT(28) thin films fabricated by pulsed laser deposition are suitable for DRAM capacitor application.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.168-168
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• 2011

정보화 사회가 도래함으로 개인별 정보 이용량이 급격히 증가하였고 스마트폰과 같은 모바일 기기의 개발로 정보 이용량이 최고치를 갱신 중이다. 이러한 흐름 속에 사람들은 빠른 처리 속도와 고도의 저장 능력을 요구하게 되고 이에 따라 새로운 Random Access Memory에 대한 연구가 활발히 진행되고 있다. 현재 Dynamic Random Access Memory (DRAM)가 눈부신 발전과 성과를 이룩하고 있지만 전원 공급이 중단 될 경우 저장된 내용들이 지워진다는 단점을 가지고 있다. DRAM의 장점에 이러한 단점을 보완할 수 있는 차세대 반도체 소자로 주목 받고 있는 것이 Magnetic Random Access Memory (MRAM)이다. DRAM에서 Capacitor와 유사한 기능을 하는 MTJ stack은 tunneling magnetoresistance (TMR) 현상을 나타내는 자기저항 박막을 이용하여 MRAM 소자에 집적된다. 본 연구에서는 MRAM의 자성 재료로 구성된 MTJ stack을 효과적으로 식각하고 우수한 식각 profile을 얻는 동시에 재증착의 문제를 해결하는데 목적을 둔다. 본 IrMn 자성 박막의 식각 연구는 유도결합 플라즈마 반응성 이온 식각 (Inductively Coupled Plasma Reactive Ion Etching: ICPRIE)법을 이용하여 진행되었다. 특히 본 연구에서는 종래의 $Cl_2$, $BCl_3$ 그리고 HBr과 같은 부식성 가스가 아닌 부식성이 없는 $CH_4$가스를 선택하여 그 농도를 변화시키면서 식각하였고 더 나아가 $O_2$를 첨가하면서 그 효과를 극대화하려고 시도하였다. IrMn 자성 박막의 식각 속도, TiN 하드 마스크에 대한 식각 선택도 그리고 profile 등이 조사되었고 최종적으로 X-ray photoelectron spectroscopy (XPS)를 이용하여 식각 메카니즘을 이해하려고 하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.5
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• pp.185-190
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• 2002

Capacitor material utilized in the downsizing passive devices and dynamic random access memory(DRAM) requires the physical and electrical properties at given area such as capacitor thickness reduction, relative dielectric constant increase, low leakage current and thermal stability. Common capacitor materials, $SiO_2$, $Si_3N_4$, $SiO_2$/$Si_3N_4$,TaN and et al., used until recently have reached their physical limits in their application to several hundred angstrom scale capacitor. $Ta_2O_{5}$ is known to be a good alternative to the existing materials for the capacitor application because of its high dielectric constant (25 ~35), low leakage current and high breakdown strength. Despite the numerous investigations of $Ta_2O_{5}$ material, there have little been established the clear understanding of the annealing effect on capacitance characteristic and conduction mechanism, design and fabrication for $Ta_2O_{5}$ film capacitor. This study presents the structure-property relationship of reactive-sputtered $Ta_2O_{5}$ MIM capacitor structure processed by annealing in a vacuum. X-ray diffraction patterns skewed the existence of amorphous phase in as-deposited condition and the formation of preferentially oriented-$Ta_2O_{5}$ in 670, $700^{\circ}C$ annealing. On 670, $700^{\circ}C$ annealing under the vacuum, the leakage current decrease and the enhanced temperature-capacitance characteristic stability. and the leakage current behavior is stable irrespective of applied electric field. The results states that keeping $Ta_2O_{5}$ annealed at vacuum gives rise to improvement of electrical characteristics in the capacitor by reducing oxygen-vacancy and the broken bond between Ta and O.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.291-294
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• 1998

The objective of this study is to deposited the preparation of STO dielectric thin films on Ag/barrier-mater/Si(N-type 100) bottom electrode using a conventional rf-magnetron sputtering technique with a ceramic target under various conditions. It is demonstrated that the leakage current of films are strongly dependent on the atmosphere during deposition and the substrate temperature. The resistivity properties of films deposited on silicon substrates were very high resistivity. Capacitance of the films properties were the highest value(1000pF) and dependent on substrate temperature.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.118-121
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• 1999

PLZT thin films were fabricated with different energy density by pulsed laser deposition. PLZT films deposited on Pt/Ti/SiO$_2$/Sr substrate. This PLZT thin films of 5000$\AA$ thickness were crystallized at $600^{\circ}C$, 200mTorr $O_2$ pressure for 2 J/$\textrm{cm}^2$ laser energy density. 14/50/50 PLZT thin film showed a maximum dielectric constant value of $\varepsilon$$_{r}$=1289.9 P-E hysteresis loop of 14/ 50/50 PLZT thin film was slim ferroelectric. Leakage current density of 14/50/50 PLZT thin film was 10/ sup -7/=A/$\textrm{cm}^2$.>.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.278-281
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• 1999

PLZT thin films on Pt/Ti/SiO$_2$/Si substrate were fabricated with different Thickness by pulsed laser deposition. 14/50/50 PLZT thin film showed a maximum dielectric constant value of $\varepsilon$$_{t}$=985 at 5000$\AA$, and $\varepsilon$$_{t}$=668 at 2000A. P-EI hysteresis loop of 14/50/50 PLZT thin film was slim ferroelectric. Leakage current density of 14/50/70 PLZT thin film was 10$^{-8}$ A/$\textrm{cm}^2$ at 2000$\AA$.EX>.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.57-57
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• 2003

High dielectric constant materials (high K) have attracted a great deal of interest because of the dramatic scaling down of DRAM capacitor reaching its physical limit in terms of reduction of thickness. Among high-K materials that can replace silicon dioxide, tantalum pentoxide (Ta2O5) thin film, with their high dielectric constant (∼25) and good step coverage, is the candidate of choice.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.527-528
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• 2010