• Title/Summary/Keyword: DMA Control

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A Data Communication Method for Real-Time Control Systems (실시간제어시스템을 위한 데이터통신방식)

  • 장태무
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.7 no.2
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    • pp.66-70
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    • 1982
  • A data communication protocol and interface between a minicomputer and remote microprocessor-based real-time controllers are proposed and designed. Practically this method was implemented on a real-time data acquisition and on-line control system with a good performance.

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Design of Synchronized Power Control Embedded System Based on Core-A Platform (Core-A 플랫폼을 이용한 동기형 전력제어 임베디드 시스템 설계)

  • Lee, Woo-Kyung;Moon, Dai-Tchul
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.6
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    • pp.1413-1421
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    • 2014
  • This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform is consisted of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. design of Embedded system is executed in Flowrian II, in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

Synchronized Power Control Embedded System Based on Core-A Platform (Core-A 플랫폼을 이용한 동기형 전력 제어 임베디드 시스템)

  • Lee, Woo-kyung;Moon, Dai-Tchul;Park, In-Hag
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.809-812
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    • 2013
  • This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform provided by Dynalith Systems consists of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. Design of Embedded system is executed in Flowrian2 of System Centroid Inc., in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

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Influence of Nitrite and Ascorbic acid on N-Nitrosamine Formation during the Fermentation of Salt-fermented Small Shrimp (새우젓 숙성중 아질산염과 아스코르브산이 N-Nitrosamine의 생성에 미치는 영향)

  • KIM Jeong-Gyun;LEE Soo-Jung;SUNG Nak-Ju
    • Korean Journal of Fisheries and Aquatic Sciences
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    • v.31 no.1
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    • pp.63-70
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    • 1998
  • The changes of contents of trimethylamine oxide nitrogen (TMAO-N), trimethylamine nitrogen (TMA-N), dimethylamine nitrogen (DMA-N), nitrite nitrogen (nitrite-N), nitrate nitrogen (nitrate-N) and N-nitrosamine (NA) of salt-fermented small shrimp were investigated during fermentation. The contents of TMAO-N decreased, while TMA-N and DMA-N increased during fermentation in all samples. Contents of nitrite-N decreased in the samples supplemented with sodium nitrite during fermentation, whereas the formation of N-nitrosodimethylamine (NDMA) increased. Treatment of ascorbic acid revealed inhibiting effort on NDMA formation compared with the control. The model system was used for the evaluation of ascorbic acid (inhibitor) or thiocyanate (promoter) on the formation of NDMA using salt-fermented small shrimp supplemented with sodium nitrite, The optimum pH for the formation of NDMA was 3.5, and ascorbic acid inhibited the formation of NDMA whereas thiocyanate promoted.

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The design of high profile H.264 intra frame encoder (H.264 하이프로파일 인트라 프레임 부호화기 설계)

  • Suh, Ki-Bum
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.11
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    • pp.2285-2291
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    • 2011
  • In this paper, H.264 high profile intra frame encoder, which integrates intra prediction, context-based adaptive variable length coding(CAVLC), and DDR2 memory control module, is proposed. The designed encoder can be operated in 440 cycle for one-macroblock. In order to verify the encoder function, we developed the reference C from JM 13.2 and verified the developed hardware using test vector generated by reference C. The designed encoder is verified in the FPGA (field programmable gate array) with operating frequency of 200 MHz for DMA (direct memory access), operating frequency of 50 MHz of Encoder module, and 25 MHz for VIM(video input module). The number of LUT is 43099, which is about 20 % of Virtex 5 XC5VLX330.

A Study of the Exclusive Embedded A/D Converter Using the Microprocessor and the Noise Decrease for the Magnetic Camera (마이크로프로세서를 이용한 자기카메라 전용 임베디드형 AD 변환기 및 잡음 감소에 관한 연구)

  • Lee, Jin-Yi;Hwang, Ji-Seong;Song, Ha-Ryong
    • Journal of the Korean Society for Nondestructive Testing
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    • v.26 no.2
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    • pp.99-107
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    • 2006
  • Magnetic nondestructive testing is very useful far detecting a crack on the surface or near of the surface of the ferromagnetic materials. The distribution of the magnetic flux leakage (DMFL) on a specimen has to be obtained quantitatively to evaluate the crack. The magnetic camera is proposed to obtain the DMFL at the large lift-off. The magnetic camera consists of a magnetic source, magnetic lens, analog to digital converters (ADCs), interface, and computer. The magnetic leakage fields or the distorted magnetic fields from the object, which are concentrated on the magnetic lens, are converted to analog electrical signals tv arrayed small magnetic sensors. These analog signals are converted to digital signals by the ADCs, and are stored, imaged, and processed by the interface and computer. However the magnetic camera has limitations with respect to converting and switching speed, full range and resolution, direct memory access (DMA), temporary storage speed and volume because common ADCs were used. Improved techniques, such as those that introduce the operational amplifier (OP-Amp), amplify the signal, reduce the connection line, and use the low pass filter (LPF) to increase the signal to noise ratio are necessary. This paper proposes the exclusive embedded ADC including OP-Amp, LPF, microprocessor and DMA circuit for the magnetic camera to satisfy the conditions mentioned above.

A Study on Interface for Image Compression Based on SOPC (SOPC 기반 영상압축을 위한 인터페이스 연구)

  • Jung, Jae-Wook;Son, Hong-Bum;Park, Seong-Mo
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.687-688
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    • 2006
  • This paper presents implementation of the lifting based DWT processor interface which the process of JPEG2000. The proposed architecture uses Excalibur device produced Altera. This study describes CIS(CMOS Image Sensor), DMA(Direct Memory Access) and DWT control logic

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Implementation of DCT using Bit Slice Signal Processor (BIT SLICE SIGNAL PROCESSOR를 이용한 DCT의 구현)

  • Kim, Dong-L.;Go, Seok-B.;Paek, Seung-K.;Lee, Tae-S.;Min, Byong-G.
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1449-1453
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    • 1987
  • A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

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A Message Transfer Scheme for Efficient Message Passing in the Highly Parallel Computer SPAX (고속병렬컴퓨터(SPAX)에서의 효율적인 메시지 전달을 위한 메시지 전송 기법)

  • 모상만;신상석;윤석한;임기욱
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.9
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    • pp.1162-1170
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    • 1995
  • In this paper, we present a message transfer scheme for efficient message passing in the hierarchically structured multiprocessor computer SPAX(Scalable Parallel Architecture computer based on X-bar network). The message transfer scheme provides interface not only with operating system but also with end users. In order to transfer two types of control message and data message efficiently, it supports both of memory-mapped transfer and DMA-based transfer. Dual-port RAMs are used as message buffers, and control and status registers provide efficient programming interface. Interlaced parity scheme is adopted for error control. If any error is detected at receiving node, errored packet is resent by sender according to retry mechanism. In conjunction with retry mechanism, watchdog timers are used to protect infinite waiting and repeated retry. The proposed message transfer scheme can be applied to input/output nodes and communication connection nodes as well as processing nodes in the SPAX.

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Monitoring of Airborne Fine Particle using SMPS in Ansan Area (SMPS(Scanning Mobility Particle Sizer)를 이용한 안산지역 대기중 초미세입자(30\~500nm) 분포연구)

  • Kim Yong-min;Ahn Kang-Ho
    • Journal of Korean Society for Atmospheric Environment
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    • v.21 no.3
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    • pp.295-301
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    • 2005
  • The fine particles in the range of $30\~500nm$ are monitored at Hanyang University campus in Ansan using house made DMA (differential mobility analyzer) and commercial CPC (condensation particle counter, TSI inc.) in SMPS mode. The monitoring period is March 16th 2004 through May 7th, 2004. During the monitoring period, Aitken nuclei mode $(30\~100nm)$ particle concentration has a tendency of increase in the morning and evening hours. However, the accumulation mode $(100\~500nm)$ particle concentration stays rather stable than that of Aitken mode.