• 전기학회논문지
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• 제56권6호
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• 전기학회논문지
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• 제58권6호
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• pp.1065-1070
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• 2009

This paper presents the new technique of modeling using Dynamic Link Library(DLL) in ElectroMagnetic Transients Program - Restructured Version(EMTP-RV) in which we have simplified the procedures of OverCurrent Relay(OCR) modeling. The DLL function is designed to allow EMTP-RV users to develop advanced program model modules and interface them directly and intimately with the EMTP-RV engine. The modeled OCR is verified by simulating the various fault cases in the distribution system. Also, the performance for the modeling of OCR using DLL is compared with that of the method using the control components of EMTP-RV and using EMTP/MODELS. The results show the validity of modeled OCR and the effectiveness of the method using DLL function.

• ETRI Journal
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• 제29권6호
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• pp.716-724
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• 2007

As ultra-wideband impulse radio (UWB-IR) uses short-duration impulse signals of nanoseconds, even a small number of timing errors can cause a detrimental effect on system performance. A delay-locked loop (DLL) is proposed to synchronize and reduce timing errors. The design of the DLL is vital for UWB systems. In this paper, an improved DLL is introduced to a UWB-IR time-hopping spread-spectrum system. Instead of using only two central correlator branches as in a conventional DLL, the proposed system uses two additional correlator branches with different delay parameters and different weight parameters. The performance of the proposed schemes with the optimal parameters is compared with that of traditional schemes through simulation: the proposed four-branch DLLs achieves less tracking jitter or a longer mean time to lose lock (MTLL) than the conventional two-branch DLLs if proper parameters are chosen.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.426-429
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• 2002

The data link layer (DLL) of Foundation Fieldbus (FF) includes both token-passing and scheduling services. Periodic data are transmitted via the scheduling service, while time-critical and time-available data are transmitted via the token-passing service. This study developed a network interface board that implements the DLL of FF. Using the network interface board, this study experimentally evaluates the delay performance of the DLL of FF. This study measured the delay performance with respect to the change of the DLL parameters of FF, and investigated the relationship between the DLL parameters and network performance. The study also compared the experimental results with the results obtained from an analytical model.

• 전자공학회논문지A
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• 제33A권3호
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• pp.1-9
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• 1996

in this paper, we analyzed CDD-DLL code tracking loop for tracking of direct-sequence spread-spectrum signals in a multipath fading channel. The multipath fading channel is modeled as two-ray rayleigh fading channel which is well applicable in a land mobile communication environments. We use trackin jitter variance and mean-time-to-lose-lick as performance measures. From the numerical resutls, it is shown that the effect of multipath fading decreases as SNR/bit increases. Also it is shown that CDD-DLL provides superior jitter performance compared with noncoherent DLL and jitter performance improvement is more significant for a two-ray rayleigh fading channel than an AWGN channel.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• 대한통합의학회지
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• 제7권3호
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• pp.61-69
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• 2019

Purpose : The purpose of this study was to investigate the effects of Straight leg lifts (SLL) and double leg lowering (DLL) exercise on abdominal muscle activity, visual analog scale (VAS), and flexibility in patients with chronic low back pain (LBP). Methods : A total of 30 LBP patients were divided into two groups: those with SLL exercise group 15 (male=8, female=7) and those with DLL exercise group 15 (male=7, female=8). Before the intervention, the abdominal muscle activity, VAS, and flexibility were measured. After 4 weeks of intervention, the above variables were measured in the same way. The SLL exercise bends the leg $45^{\circ}$ in the supine position, and the DLL exercise was performed as opposed to SLL. At this time, the pressure biofeedback unit (PBU) was placed behind the lumbar to reduce the instability of the pelvis and muscles. The subjects were instructed to use the PBU to maintain the target pressure determined (40 mmHg) during the exercise. Results : The external oblique (EO), internal oblique (IO), and transverse abdominis (TrA) were significantly different in the SLL and DLL group, and EO, IO, and TrA activity improved more significantly increased in the DLL than SLL group (p<.05). The results on the VAS and flexibility were significantly different both group (p<.05). However, there was no significant difference between the groups (p>.05). Conclusion : SLL and DLL exercises in patients with LBP were able to confirm the increased activity of the abdominal muscles, decreased pain, and increased flexibility of the waist. In addition, DLL exercise is more effective in patients with LBP in terms of muscle activity.

• 전기전자학회논문지
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• 제26권3호
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• pp.380-388
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• 2022

전통적인 악성코드 탐지 기술은 알려진 악성코드를 수집하고 특성을 분석한 후, 분석된 정보를 블랙리스트로 생성하고, 이를 기반으로 시스템 내의 프로그램들을 검사하여 악성코드 여부를 판별한다. 그러나 이러한 접근 방법은 알려진 악성코드의 탐지에는 효과적일 수 있으나 알려지지 않았거나 기존 악성코드의 변종에 대해서는 효과적으로 대응하기 어렵다. 또한, 시스템 내의 모든 프로그램을 감시하기 때문에 시스템의 성능을 저하시킬 수 있다. 이러한 문제점들을 해결하기 위하여 악성코드의 주요 행위를 분석하고 대응하기 위한 다양한 방안들이 제안되고 있다. 랜섬웨어는 사용자의 파일에 접근하여 암호화한다. 이러한 동작특성을 이용하여 시스템의 사용자 파일에 접근하는 정상적인 프로그램들을 화이트리스트로 관리하고 파일 접근을 제어하는 방안이 제안되었다. 그러나 화이트리스트에 등록된 정상 프로그램에 DLL(Dynamic-Link Library) 삽입 공격을 수행하여 악성 행위를 수행하게 할 수 있다는 문제점이 지적되었다. 본 논문에서는 화이트리스트 기반 접근통제 기술이 이러한 DLL 삽입 공격에 효과적으로 대응할 수 있는 방안을 제안한다.

• 한국산업정보학회논문지
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• 제18권5호
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• pp.9-14
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• 2013

본 논문은 DLL 기술을 사용하여서 낮은 위상잡음을 갖는 주파수 체배기를 설계 하였다. VCDL은 공통모드 잡음을 줄이기 위해서 차동구조를 이용하여 설계 되었다. 이번 설계는 65nm, 1.2V TSMC CMOS 공정을 이용 하였고, 동작 주파수 범위는 10MHz에서 24MHz로 측정되었다. TCXO를 기준 주파수로 사용하여 위상잡음을 측정하였을 때 38.4MHz의 출력에서 1MHz offset 기준으로 -125dBc/Hz가 측정되었다. 총 면적은 $0.032mm^2$을 사용하였고, 출력 버퍼를 포함하여 총 1.8mA의 전류를 칩에서 소비하였다.

• 전기전자학회논문지
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• 제15권1호
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• pp.23-28
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• 2011

본 논문에서는 CMOS 회로를 이용한 스프레드 스펙트럼 클록 발생기(SSCG)를 제안하고 구현하였다. 지연고정루프(DLL)의 저역통과필터(LPF)에 스프레드 스펙트럼 클럭 변조 로직에 의해 조절되는 전하펌프를 연결하여 전압 제어지연로직(VCDL)에 가해지는 제어전압을 조절함으로써 주파수의 변화를 유도하는 방법을 사용하였다. 이와 같은 구조에서는 변조 비율을 조절하기 위한 부가적인 회로가 필요없기 때문에 레이아웃 면적이 작아지게 되고 전력소모가 작아지는 장점을 갖는다. 스프레드 스펙트럼 클록 발생기는 UMC 0.25um 공정을 이용하여 시뮬레이션 및 레이아웃을 수행하였으며 전체 면적은 290um${\times}$120um^2 이다.