• Title/Summary/Keyword: DF-DPD

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A Performance Analysis of DF-DPD and DPD-RGPR (DF-DPD와 DPD-RGPR에 대한 성능 분석)

  • Jeong, Jin-Doo;Jin, Yong-Sun;Chong, Jong-Wha
    • 전자공학회논문지 IE
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    • v.47 no.4
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    • pp.39-47
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    • 2010
  • This paper proposes a numerical analysis to prove that the performance of the differential phase detections (DPDs) with the decision feedback, such as the decision feedback DPD (DF-DPD) and the DPD with recursively generated phase reference (DPD-RGPR), approach the performance of the coherent detection with differential decoding. The conventional differential phase detection for M-ary DPSK can make the receiver architecture simple, while it can make the bit-error rate (BER) performance poor because of the previous noisy phase as a reference phase. To improve the BER performance of the conventional differential detection, multiple symbol differential detection methods, including DF-DPD and DPD-RGPR, have been proposed. However, the studies on the analysis and on the comparison of these methods have been little performed. Then, this paper mathematically intends to analyze and compare the performance of the DPDs with the decision feedback. The analysis results show that the DPDs with the decision feedback can have the performance equal to that of the coherent detection with differential decoding and be available for the noncoherent detection in the improved performance. Considering the hardware complexity, the DPD RGPR with the simple detection process by using the recursively generated phase reference can be more simply implemented than the DF-DPD based on the architecture whose complexity increases according to the increasing detection length.

Architecture for High-speed Data Processing of DF-DPD (DF-DPD의 고속 데이터 처리 구조)

  • Kim, Yeong-Sam;Jeong, Jin-Doo;Yun, Sang-Hun;Jang, Seong-Hyeon;Jeong, Man-Hee;Oh, Dae-Gun;Chong, Jong-Wha
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.373-374
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    • 2008
  • This paper proposes an architecture for high-speed data processing of the DF-DPD. The DF-DPD have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, an architecture is proposed for high-speed data processing of the differential phase detectors with decision feedback in the DF-DPD.

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A VLSI Architecture for Novel Decision Feedback Differential Phase Detection with an Accumulator

  • Kim, Chang-Kon;Chong, Jong-Wha
    • ETRI Journal
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    • v.24 no.2
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    • pp.161-171
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    • 2002
  • This paper proposes a novel decision feedback differential phase detection (DF-DPD) for M-ary DPSK. A conventional differential phase detection method for M-ary Differential Phase Shift Keying (DPSK) can simplify the receiver architecture. However, it possesses a poorer bit error rate (BER) performance than coherent detection because of the prior noisy phase sample. Multiple-symbol differential detection methods, such as maximum likelihood differential phase detection, Viterbi-DPD, and DF-DPD using L-1 previous detected symbols, have attempted to improve BER performance. As the detection length, L, increases, the BER performance of the DF-DPD improves but the complexity of the architecture increases dramatically. This paper proposes a simplified DF-DPD architecture replacing the conventional delay and additional architecture with an accumulator. The proposed architecture also improves BER performance by minimizing the current differential phase noise through the accumulation of previous differential phase noise samples. The simulation results show that the BER performance of the proposed architecture approaches that of a coherent detection with differential decoding.

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A VLSI Design for High-speed Data Processing of Differential Phase Detectors with Decision Feedback (결정 궤환 구조를 갖는 차동 위상 검출기의 고속 데이터 처리를 위한 VLSI 설계)

  • Kim, Chang-Gon;Jeong, Jeong-Hwa
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.74-86
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    • 2002
  • This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.