• Korean Journal of Computational Design and Engineering
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• v.15 no.4
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• pp.279-288
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• 2010

In this paper, a DEVS(Discrete EVent Systems Specification)-HLA(High Level Architecture) interface was developed in order to perform the simulation using the combined discrete event and discrete time simulation model architecture in a distributed environment. The developed interface connects the combined simulation model with the HLA/RTI(Run-Time Infrastructure) which is an international standard middleware for distributed simulation. The interface consists of an interface model, a model interpreter, and a distributed environment interpreter. The interface model was defined by using the combined simulation architecture in order to easily connect the existing combined simulation model without modification with the HLA/RTI. The model interpreter takes charge of data transmission between the interface model and the combined simulation model. The distributed environment interpreter takes charge of data transmission between the interface model and the HLA/RTI. To evaluate the applicability of the developed interface, it was applied to the diving simulation of a submarine in a distributed environment. The result shows that a simulation result in a distributed environment using the interface is the same to the result in a single computing environment.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.484-484
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• 2001

The sophistication of current software applications results in the increasing cost fur software development time. The component-based software development framework is proposed to overcome the difficulty and time-consuming requirements by modularity and reusability. As is the general software case, a component-based simulation framework encourages the reusability of the real system model based on the modularity of the applied simulation methodology. This paper presents a component-based simulation environment that is based on the DEVS/COM run-time infrastructure. The DEVS (Discrete Event System Specification) formalism provides a formal modeling and simulation framework for the generic dynamic systems [1] and Microsoft's COM (Component Object Model) is one of the strongest competitor fur the component standard. The reusability by the DEVS/COM simulation environment saves model development time remarkably and component technology make simulator itself to be a subparts of real application.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.75-88
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• 1994

Discrete event modeling is finding ever more application to anlysis and design of complex manufacturing, communication, computer systems, etc. This paper shows how packet network systems may be advantageously represented as DEVS (Discrete Event System Specification) models by employing System Entity structure / Model base (SES/MB) framework developed by Zeigler. DEVS models and network structure representations support a strong basis for performance analysis of packet network systems. This approach is illustated in a typical packet network example with several routing strategies.

• Journal of the Korea Society for Simulation
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• v.8 no.4
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• pp.109-124
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• 1999

The major objective of this research is to design and build the variable structure DEVS modeling & simulation framework. To do this, we have proposed the direct message passing mechanism between the model and its simulator to deal with the structural demand from the model during the simulation. In this approach, four types of basic messages are introduced for the vertical(creation/deletion of the child) and horizontal(creation/deletion of the brother) structural changes. Proposed methodology has been successfully applied to the multi-processor system and the forest fire information system.

• Proceedings of the Korea Society for Simulation Conference
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• 2002.05a
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• pp.253-258
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• 2002

This paper proposes a methodology for development of protocol models. The methodology attempts to employ two modeling environments in models development, NS2 and DEVSim++, which will interoperate during simulation. NS2 is a widely used network simulator in protocol research, which employs an informal modeling approach. Within the approach time and state information of protocol models are not explicitly described, thus being hard to validate model. On the other hand the DEVS formalism is a mathematical framework for modeling a discrete event system in a hierarchical, modular manner. In DEVS, model's time and state information is described explicitly, By using DEVS formalism, models can easily be validated and errors in the modeling stage can be reduced. However, the DEVS simulator, DEVSim++, supports a small amount of models library which are required to build simulation models of general communication network. Although NS2 employs an informal modeling approach and models validation is difficult, it supports abundant models library validated by experimental users. Thus, combination of DEVS models and NS2 models may be an effective solution for network modeling. Such combination requires interoperation between DEVSim++ simulator and NS2 simulator. This paper develops an environment for such interoperation. Correctness and effectiveness of the implemented interoperation environment have been validated by simulation of UDP and TCP models.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.1029-1036
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• 2007

State explosion is a well-known problem that impedes analysis md testing of discrete event systems, thus making the verification of large systems intrinsically difficult job. This paper suggests a hierarchical verification methodology of untimed DEVS model which can alleviate the state explosion problem. The method is a repetitive procedure of designing and verifying between the upper level and the lower level models abstracting away the unnecessary information with respect to a given verification task. A small example was employed to show our suggested method in detail.

• Journal of the Korea Society for Simulation
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• v.1 no.1
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• pp.64-76
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• 1992

The DEVS(discrete event system specificaition) formalism specifies a discrete event system in a hierarchical, modular form. DEVSIM++ is a C++based general purpose DEVS abstract simulator which can simulate systems modeled by the DEVS formalism in a sequential environment. This paper describes P-DEVSIM++which is a parallel version of DEVSIM++ . In P-DEVSIM++, the external and internal event of DEVS models can by processed in parallel. For such processing, we propose a parallel, distributed optimistic simulation algorithm based on the Time Warp approach. However, the proposed algorithm localizes the rollback of a model within itself, not possible in the standard Time Warp approach. An advantage of such localization is that the simulation time may be reduced. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• Journal of the Korea Society for Simulation
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• v.18 no.3
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• pp.113-122
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• 2009

Software is getting more complex due to a variety of requirements that include desired functions and properties. Therefore, verifying and testing the software are complicated problems. Moreover, if the software is already implemented, inserting and deleting tracing/logging code into the source code may cause several problems, such as the code tangling and the code scattering problems. This paper proposes the Aspect DEVS Verification Framework which supports the verification and testing process. The Aspect DEVS Verification Framework utilizes Aspect Oriented Programming features to handle the code tangling and the code scattering problems. By applying aspect oriented features, a user can find and fix the inconsistency between requirement and implementation of a software without suffering the problems. The first step of the verification process is the building aspect code to make a software act as a generator. The second step is developing a requirement specification using DEVS diagrams and implementing it using the DEVSIM++. The final step is comparing the event traces from the software with the possible execution sequences from DEVS model.

• Journal of the Korea Society for Simulation
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• v.13 no.3
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• pp.43-54
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• 2004

Studies of Internet algorithms or policies require experiments on the real large-scale networks. But practical problems with large real networks make them difficult. Instead many researchers use simulations on the Internet topology models. So, It is Important that study about topology model that reflect characteristic of the internet exactly. We propose new topology model which reflect of hierarchical network and addition, removal of nodes and accompanied change of topologies. In the modeling scheme for network generation, we applied DEVS formalism and analyzed the topologies generated by our algorithms.

• Journal of Korea Multimedia Society
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• v.22 no.9
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• pp.1080-1090
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• 2019

The digital informational era of the 21st century requires the fostering of human resource in the field of software with creativity and personality. This paper deals with the educating method in programming course for non-majors which fosters creativity for problem solving ability and personality using cooperative interaction to build communication ability. We also seek to build a model through DEVS methodology for creative problem solving and analyze the effects of programming education for the cultivation of creativity and personality. Our proposed model is expected to be used as a guide to establish creativity and personality for human resource cultivation in programming education.