• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.8
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• pp.816-823
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• 2008

This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.

• Journal of Advanced Navigation Technology
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• v.14 no.6
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• pp.916-927
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• 2010

In this paper, we analyze the performance of the parity cache enabled RAID level-5 via the simulation. This RAID system consists of the DDR memory-based storage devices. To do this, we develop the simulation model and suggest the basic performance analysis data which we want to get via the simulation. And we implement the simulator based on the simulation model and execute the simulator. From the result of the simulation, we expect that the parity cache enabled RAID level-5 configured by the DDR memory based storage devices has the positive effectiveness to the enhancing of the storage system performance if the storage access patterns of applications are tuned.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1104-1110
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will Developed memory controller using punctuality guarantee algorithm. As the results, show that when we adopt the DDR2 SDRAM, we can get the benefits of saving 13.5 times and 5.3 times in cost and space, respectively, compared to the SRAM.

• Journal of KIISE
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• v.44 no.2
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• pp.124-131
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• 2017

The emerging next-generation manycore processors for high-performance computing are equipped with a high-bandwidth on-package memory along with the traditional host memory. The Multi-Channel DRAM (MCDRAM), for example, is the on-package memory of the Intel Xeon Phi Knights Landing (KNL) processor, and theoretically provides a four-times-higher bandwidth than the conventional DDR4 memory. In this paper, we suggest a mechanism to exploit MCDRAM for improving the performance of MPI intra-node communication. The experiment results show that the MPI intra-node communication performance can be improved by up to 272 % compared with the case where the DDR4 is utilized. Moreover, we analyze not only the performance impact of different MCDRAM-utilization mechanisms, but also that of core affinity for processes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.540-543
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• 2010

POWER PC series are common to the Central Processing Unit for Military Single Board Computer. Among them, G4 group, which contains the 74xx series supported by Freescale manufacturer is mainly used in the Military applications. We focus on the Interface between memory and controller. PCB stacking method, component routing, impedance matching and harsh environment for Military spec are the main constraints for implementation. Also, we developed memory as a module for the consideration of Military environments. The overall type of SBC should be designed by the form of 6U VME or 3U VME.

• Electronics and Telecommunications Trends
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• v.15 no.6 s.66
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• pp.118-127
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• 2000

DRAM 메모리는 FPM DRAM, EDO DRAM, SDRAM, DDR/DDR II SDRAM, RDRAM, FCRAM 등의 범용 구조와 VRAM, WRAM, CDRAM, MDRAM 등의 디스플레이용 구조로 크게 나눌 수 있다. DRAM의 가장 큰 어플리케이션은 PC 부문이며, DRAM은 각 어플리케이션별 비용/성능 트레이드 오프에 따라 선호되는 구조가 달라서 당분간은 여러 구조가 공존할 것으로 보인다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.136-142
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• 2013

CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.136-139
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.521-527
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• 2011

POWER PC series are common to the Central Processing Unit for Military Single Board Computer. Among them, G4 group, which contains the 74xx series supported by Freescale manufacturer is mainly used in the Military applications. We focus on the Interface between memory and controller. PCB stacking method, component routing, impedance matching and harsh environment for Military spec are the main constraints for implementation. Also, we developed memory as a module for the consideration of Military environments. The overall type of SBC should be designed by the form of 6U VME or 3U VME. Therefore this study suggests the electrically optimum Interface matching, Artwork technology based on the signal cross over and PCB stacking method on the harsh environment.