• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.48-58
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• 2006

This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.97-102
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• 2008

In this paper, we address the OFDM based on DFT or DCT in Cognitive Radio system. An adaptive OFDM based on DFT or DCT in Cognitive Radio system has the capacity to nullify individual carriers to avoid interference to the licensed users. Therefore, there could be a considerably large number of zero-valued inputs/outputs for the IDFT/DFT or IDCT/DCT on the OFDM transceiver. Hence, the standard methods of DFT and DCT are no longer efficient due to the wasted operations on zero. Based on this observation, we present a transform decomposition on two dimensional(2-D) systolic array for IDFT/DFT and IDCT/DCT, this algorithm can achieve an efficient computation for OFDM in Cognitive Radio system

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1998.06a
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• pp.189-192
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• 1998

본 논문은 DCT (Discrete Cosine Transform) 영역에서의 압축 동영상 하향 전환기법 (down conversion)을 제안한다. DCT 영역에서의 하향 전환이 완전 복호화한 후 공간 영역에서 하향 전환하는 것보다 계산량 측면에서 상당한 이점이 있다. 또한 복호기 루프 내에서 영상 크기가 줄기 때문에 메모리의 부담을 덜 수 있다. 가장 간다한 방법으로서 복원된 영상의 화질이 약잔 떨어지더라도 계산량과 메모리를 줄이기 위해 8x8 DCT 블록의 저주파 영역의 4x4 DCT 계수만을 추출하여 4x4 IDCT하는 기법이 널리 알려져 있다. 본 논문에서는 변형된 4x4 IDCT 기저 함수를 이용한 새로운 DCT 영역에서의 하향 전환 기법을 제안한다. 모의실험을 통해 제안한 기법이 기존의 DCT 영역에서의 하향 전환기법과 같은 계산량 및 메모리로 향상된 PSNR을 갖는다는 것을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1928-1934
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• 1993

This paper presents a fast algorithm of integer discrete cosine transform(IDCT) allowing VLSI implementation by integer arithmetic. The proposed fast algorithm has been developed using Chen`s matrix decomposition in DCT, and requires less number of arithmetic operations compared to the IDCT. In the presented algorithm, the number of addition number is the same as the one of Chen`s algorithm if DCT, and the number of multiplication if the same as that in DCT at N=8 but drastically decreasing when N is above 8. In addition, the drawbacks of DCT such as performance degradation at the finite length arithmetic could be overcome by the IDCT.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.188-198
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• 1994

The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.136-139
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• 2004

This thesis is realization of embedded system that of MPEG-2 down conversion using IDCT. A method for down conversion of MPEG compressed video is to perform low-pass filtering and sub-sampling after full decompression. However, this method is need large memory and high computational complexity. Recent research has been focussed on the down conversion in the DCT domain. But DCT method is reduced image qualify. The embedded system is require low complexity, and high speed algorithm. When applied to embedded system that down conversion method, DCT method is played average 29 frame per second, and better 25% than spatial-domain down conversion.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.880-894
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• 1997

In this paper,we propose a new algorithm to perform DCT(Discrete Cosine Transform) withn the area reduced by prdeicting position of quantization coefficients to be zero.This proposed algorithm not only decreases the enoding time and the decoding time by reducing computation amount of FDCT(Forward DCT)and IDCT(Inverse DCT) but also increases comprossion ratio by performing each diffirent horizontal- vereical zig-zag scan assording to the calssified block size for each block on the huffiman coeing.Traditional image coding method performs the samd DCT computation and zig-zag scan over all blocks,however this proposed algorthm reduces FDCT computation time by setting to zero insted of computing DCT for quantization codfficients outside classfified block size on the encoding.Also,the algorithm reduces IDCT computation the by performing IDCT for only dequantization coefficients within calssified block size on the decoding.In addition, the algorithm reduces Run-Length by carrying out horizontal-vertical zig-zag scan approriate to the slassified block chraateristics,thus providing the improverment of the compression ratio,On the on ther hand,this proposed algorithm can be applied to 16*16 block processing in which the compression ratio and the image resolution are optimal but the encoding time and the decoding time take long.Also,the algorithm can be extended to motion image coding requirng real time processing.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.157-160
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• 2000

본 논문에서는 DVCR용 2-4-8 DCT core의 VSIA(Virtual Socket Interface Allience) 2.2 compliant IP의 구현에 대하여 기술한다. 본 논문에서 기술한 2-4-8 DCT/IDCT core는 Soft IP이며, VSIA의 deliverable document ver. 2.2에서 정의한 Soft-IP에 대한 72가지의 필수 항목, 조건부 필수 항목, 권고 항목 등의 전달물을 각 DWG(Development Working Group)의 사양에서 정의하고 있는 규격에 맞추어 가공하였다. 또한 본 논문에서는 Soft-IP에 대한 VSIA 권고안 및 VSIA deliverable list에 대하여 기술하고, VSIA compliant IP화를 위한 방법에 대하여 설명하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.773-778
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• 1993

A new approach is proposed for the DCT which is widely utilized in the image processing, The approach replaces mutiplications with shift and additions, In the image restored by the proposed DCT and IDCT, no visible degration is observed and PSNR(Peak to Peak Signal to Noise Ratio) is greater than 35 dB for all cases, proving the usefulness of the proposal.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.30-32
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• 2000

내적을 계산하는데 있어서 Distributed Arithmetic(DA)을 사용하면 곱셈기를 사용하는 것보다 소비전력 및 크기를 효율적으로 줄일 수 있고, 고속동작이 가능한 회로구현이 쉽기 때문에 신호처리 시스템 설계에 많이 사용하고 있다. DA에는 롬-기반 DA와 가산기-기반 DA를 이용한 방법이 있는데, 가산기-기반 DA는 Sharing property와 계수의 Spare non-zero bit property를 최대한 이용하여 설계가 가능하기 때문에 크기 및 동작속도 측면에서 효율적인 구현이 가능하다. 본 논문에서는 가산기-기반 DA의 이러한 특성을 최대한 이용하여 멀티미디어 신호처리에 적합한 DCT/IDCT 프로세서를 설계하였고 다른 구조 및 롬-기반 DA와 비교 평가해본 결과 크기 및 속도 측면에서 효율적인 결과를 얻었다.