• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.1
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• pp.124-131
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• 1997

There have been many demands for th ereal-time image compression. The image compression systems have a wide range of applications. However, real-time encoding is hard to implement because it needs a large amount of computations. In particular, the discrete cosine transform (DCT) and motion estimatio require a large number of arithmetic oeprations compared to other algorithms in MPEG-2. The conventional fasdt DCT algorithms have focused on the reduction of the number of additions more cycles and more expense in realization. Because TMS320C80 has special structure, new approach for implementation of DCT is suggested. The selection of adaptive algorithm and optimization is requried TMS320C80 are analyzed an dsome adaptive DCT algorithms are selected. The DCT algorithms are optimized and implemented. Chens and lees DCT algorithms among various fast algorithms are selected because 1-D approach is effective in the view of th einternal structure of TMS320C80. According to the simulation result, Lees algorithm is more effective in speed and has little difference in precision. On the basis of the result, the possibility of DCT implementation for real-time MPEG-2 system is verified and the required number of the processor, called advanced DSP, is decided for real-time MPEG-2 encoding and decoding.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.105-106
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• 2011

전력계통에서 비선형부하와 시변부하 사용의 증가 및 분산전원의 보급 증가로 전력품질(power quality)에 대한 관심이 증대되고 있다. 전력계통에서 전력품질은 전력신호를 통해 모니터링이 가능하다. 하지만 전력신호 상시 관측을 통한 전력품 모니터링은 많은 신호 데이터양이 필요하여 전력 신호 압축이 요구된다. 이에 따라 본 연구에서는 신호 압축 성능이 우수한 DCT(discrete cosine transform)기법을 이용하여 전력신호를 압축, 복원하는 방법을 제안한다. 그리고 DSP (digital signal processor) 보드를 통해서 압축 저장 된 신호를 오차 범위 5% 이내로 복원한다. 따라서 정전과 같은 이벤트(event)가 발생하였을 때 특정시간, 장소에서의 전압과 전류 파형을 볼 수 있게 한다. IEC 61000-4-30, IEEE std 1159에 근거하여 Matlab 프로그램 상에서의 성능을 평가하고 DSP보드를 이용하여 DCT를 이용한 데이터압축 시스템을 구현하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.730-732
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• 2005

최근 이미지 압축, 워터마킹 또는 스케일러블 비디오 코딩 분야에서 DCT와 DWT 연산을 선택적으로 사용하거나, 혼합하여 사용하는 경우가 늘어나고 있다. 이러한 두개의 연산을 사용하는 방법은 소프트웨어적인 프로그램을 사용하거나 하드웨어를 따로 구현하여 사용하였다. 본 연구에서는 하나의 모듈로 두개의 연산을 수행할 수 있는 재구성 하드웨어를 제안한다. 또한 DCT와 DWT연산에 있어서, 가장 많은 연산을 수행하는 부분은 계수(Coefficient)값과 입력 값의 내적 연산(Inner Product)을 수행하는 것인데, 이 내적연산을 하는데 있어서 곱셈기를 사용하지 않는 분산연산을 사용함으로써 연산의 복잡도를 줄이고, 하드웨어의 속도를 빠르게 하였다. 실험 환경은 Altera FPGA를 사용한 Excalibur_ARM (EPXA10F1020Cl) 보드를 이용하여 구현하였으며, 동작속도는 47.85MHz이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.63-72
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• 2007

In this paper, we propose a novel reconfigurable coprocessor for multimedia mobile terminals. Because most of multimedia operations require fast operations of large amount of data in the limited clock frequency, it is necessary to enhance the performance of the embedded processor that is widely used in current multimedia mobile terminals. Therefore, we proposed and have designed the coprocessor which had the ability of fast operations of multimedia data. The proposed coprocessor was not only reconfigurable, but also flexible and expandable. The proposed coprocessor has been designed by using VHDL and compared with previous reconfigurable coprocessors and a commercial embedded processor in architecture and speed. As a result of the architectural comparison, the proposed coprocessor had better structure in terms of hardware size and flexibility. Also, the simulation results of DCT application showed that the proposed coprocessor was 26 times faster than a commercial ARM processor and 11 times faster than the ARM processor with fast DCT core.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.9
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• pp.1207-1214
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• 1995

We present an optimized integer cosine transform(OICT) as an alternative approach to the conventional discrete cosine transform(DCT), and its fast computational algorithm. In the actual implementation of the OICT, we have used the techniques similar to those of the orthogonal integer transform(OIT). The normalization factors are approximated to single one while keeping the reconstruction error at the best tolerable level. By obtaining a single normalization factor, both forward and inverse transform are performed using only the integers. However, there are so many sets of integers that are selected in the above manner, the best OICT matrix obtained through value minimizing the Hibert-Schmidt norm and achieving fast computational algorithm. Using matrix decomposing, a fast algorithm for efficient computation of the order-8 OICT is developed, which is minimized to 20 integer multiplications. This enables us to implement a high performance 2-D DCT processor by replacing the floating point operations by the integer number operations. We have also run the simulation to test the performance of the order-8 OICT with the transform efficiency, maximum reducible bits, and mean square error for the Wiener filter. When the results are compared to those of the DCT and OIT, the OICT has out-performed them all. Furthermore, when the conventional DCT coefficients are reduced to 7-bit as those of the OICT, the resulting reconstructed images were critically impaired losing the orthogonal property of the original DCT. However, the 7-bit OICT maintains a zero mean square reconstruction error.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.116-119
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• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.30-32
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• 2000

내적을 계산하는데 있어서 Distributed Arithmetic(DA)을 사용하면 곱셈기를 사용하는 것보다 소비전력 및 크기를 효율적으로 줄일 수 있고, 고속동작이 가능한 회로구현이 쉽기 때문에 신호처리 시스템 설계에 많이 사용하고 있다. DA에는 롬-기반 DA와 가산기-기반 DA를 이용한 방법이 있는데, 가산기-기반 DA는 Sharing property와 계수의 Spare non-zero bit property를 최대한 이용하여 설계가 가능하기 때문에 크기 및 동작속도 측면에서 효율적인 구현이 가능하다. 본 논문에서는 가산기-기반 DA의 이러한 특성을 최대한 이용하여 멀티미디어 신호처리에 적합한 DCT/IDCT 프로세서를 설계하였고 다른 구조 및 롬-기반 DA와 비교 평가해본 결과 크기 및 속도 측면에서 효율적인 결과를 얻었다.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.1-7
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• 1999

We present VLSI architecture for a high performance 2-D DCT processor which is used compressing system of real time image processing or HDTV using fast computational algorithm of the Optimized Integer Cosine Transform(OICT). The coefficients of the OICT are integer, so the OICT performs only the integer operations for both forward and inverse transform. Therefore the proposed architecture could be greatly enhanced in improving the speed, reduced the hardware cost considerably by replacing the multiplication operations with shift and addition operations compared with DCT which performs floating-point operations.