• Title/Summary/Keyword: DC.Amplifier

검색결과 317건 처리시간 0.022초

Ku-band에서의 LNB 모듈을 위한 LNA 설계에 관한 연구 (A study on the design of LNA for Ku-band LNB module)

  • 곽용수;정태경;김형석
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 하계학술대회 논문집 C
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    • pp.2034-2036
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    • 2004
  • In this paper, a low noise amplifier (LNA) in receiver of Low Noise Block Down Converter (LNB) for direct broadcasting service (DBS) is implemented by using GaAs HEMT. The LNA is designed for operation between 10.7GHz-12.7GHz. The LNA consists of input, output matching circuits, DC-blocks and RF-chokes. Simulation result of the LNA shows that a noise figure is less than 1.4dB and a gain is greater than 9.2dB in the bandwidth of 10.7 to 12.7GHz with good flatness of 0.1dB.

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Demonstration of CSRZ Signal Generator Using Single-Stage Mach-Zehnder Modulator and Wideband CMOS Signal Mixer

  • Kang, Sae-Kyoung;Lee, Dong-Soo;Cho, Hyun-Woo;Ko, Je-Soo
    • ETRI Journal
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    • 제30권2호
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    • pp.249-254
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    • 2008
  • In this paper, we demonstrate an electrically band-limited carrier-suppressed return-to-zero (EB-CSRZ) signal generator operating up to a 10 Gbps data rate comprising a single-stage Mach-Zehnder modulator and a wideband signal mixer. The wideband signal mixer comprises inverter stages, a mixing stage, and a gain amplifier. It is implemented by using a 0.13 ${\mu}m$ CMOS technology. Its transmission response shows a frequency range from DC to 6.4 GHz, and the isolation response between data and clock signals is about 21 dB at 6.4 GHz. Experimental results show optical spectral narrowing due to incorporating an electrical band-limiting filter and some waveform distortion due to bandwidth limitation by the filter. At 10 Gbps transmission, the chromatic dispersion tolerance of the EB-CSRZ signal is better than that of NRZ-modulated signal in single-mode fiber.

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Cylindrical Silicon Nanowire Transistor Modeling Based on Adaptive Neuro-Fuzzy Inference System (ANFIS)

  • Rostamimonfared, Jalal;Talebbaigy, Abolfazl;Esmaeili, Teamour;Fazeli, Mehdi;Kazemzadeh, Atena
    • Journal of Electrical Engineering and Technology
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    • 제8권5호
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    • pp.1163-1168
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    • 2013
  • In this paper, Adaptive Neuro-Fuzzy Inference System (ANFIS) is applied for modeling and simulation of DC characteristic of cylindrical Silicon Nanowire Transistor (SNWT). Device Geometry parameters, terminal voltages, temperature and output current were selected as the main factors of modeling. The results obtained are compared with numerical method and a good match has been observed between them, which represent accuracy of model. Finally, we imported the ANFIS model as a voltage controlled current source in a circuit simulator like HSPICE and simulated a SNWT inverter and common-source amplifier by this model.

궤적 기억이 가능한 용접선 추적장치의 개발 (A Development of Seam Tracker by one Chip Microprocessor)

  • 안병원;노창주;박상길
    • 수산해양기술연구
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    • 제32권1호
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    • pp.78-84
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    • 1996
  • Recently, the fact that welding conditions are dangerous for men and the shapes of seams are complex enforced the welding system to be automatic. In order to obtain this target, are chip Microprocessor controlled welding system is devised in this study. The tracking of seam shape is achieved by applying a differential transformer and by using a program developed. This welding system mainly consists of a sensor, the differential transformer, a servo power amplifier, a control system, and DC motors. It is verified that the developed welding system is able to track three kinds of seam shapes.

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방사선 펄스의 고안정 계측회로 설계 (Design of a High Stable Measuring Circuit for Radioactive Pulses)

  • 송재용;한주섭;천상규;길경석
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2000년도 추계종합학술대회
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    • pp.577-580
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    • 2000
  • The aim of this paper is to develop a high stable measuring device for radioactive pulses. The device consists of a high voltage supply unit using a fly-back converter principle, and a pulse detection unit for gamma-rays and neutrons. The high voltage supply unit designed can generate DC voltage up to 1,500v at 5V-input, and have a series voltage regulator to maintain the output voltage constantly, resulting in less than 1.63% of voltage regulation. The pulse detection parts consists of an active integrator, a pole-zero circuit, and a 3-stage amplifier of 60 dB, and its frequency bandwidth is from 37 Hz to 300 kHz. From the experimental results, it is confirmed that the measuring device can count at least 10,000 pulses in a second.

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무선 통신을 위한 고효율 CMOS 전력 증폭기 (High efficiency CMOS power amplifier for wireless applications)

  • 유창식
    • 한국통신학회논문지
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    • 제26권10B호
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    • pp.1475-1481
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    • 2001
  • 무선 통신을 위한 전력 증폭기를 0.25$\mu\textrm{m}$ CMOS 공정으로 구현하였다. 전력 효율을 증가시키기 위하여 class-E 구조를 사용하여 soft-switching 특성을 활용하였다. Class-E 부하 회로의 DC-feed 인덕터는 유한한 값을 갖도록 하여 RF-choke을 사용하는 경우에 비해 동일한 전력과 공급 전압에 대해 필요로 하는 부하 저항의 크기를 증가시킴으로써 전력 효율을 더욱 증가시킬 수 있었다. 또한 common-gate switching 방법을 사용하여 기존의 switching 방법에 비해 허용되는 공급 전압의 크기를 두배 정도 증가시킬 수 있도록 하였다. 이러한 기법을 사용함으로써 900MHz의 주파수에서 공급 전압이 1.8V일 때 트랜지스터에 아무런 전압 stress를 가하지 않고 0.9W의 전력을 41%의 효율(power added efficiency, PAE)을 가지면서 50Ω 부하에 전달함을 확인하였다.

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전압-제어 CMOS OTA와 이를 이용한 동조 여파기 설계 (A Design of Voltage-Controlled CMOS OTA and Its Application to Tunable Filters)

  • 차형우;정원섭
    • 대한전자공학회논문지
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    • 제27권8호
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    • pp.1260-1264
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    • 1990
  • A voltage controlled CMOS operational transconductance amplifier (OTA), whose transconductance is directly proportional to the DC bias voltage, has been designed for many electronic circuit applications. It consists of a differential pair and three ourrent mirrors. The SPICE simulation shows that the conversion sensitivity of the OTA is 41.817 \ulcornerho/V and the linearity error is less than 0.402% over a bias voltage range from -2. OV to 1. OV. Electrically tunalble filters based on voltage controlled impedances, which are realized with OTA's, also have been designed. The SPICE simulation shows that a second-order bandpass filter, whose center frequency is 23KHz at -1. OV, has the conversion sensitivity 6.6KHz/V and the linearity error less than 0.822% over a voltage range from -2.OV tp 1.OV, Tne OTA has been laid out with the 3\ulcorner n-well CMOS design rule adopted in ISRC (inter-university semiconductor research center). The chip size was about $0.756x0.945mm^2$.

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Circuit Design of DRAM for Mobile Generation

  • Sim, Jae-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제7권1호
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    • pp.1-10
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    • 2007
  • In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bitline sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered.

LNB 수신단의 LNA 설계에 관한 연구 (A Ku-band LNA for LNB module)

  • 곽용수;김형석
    • 한국정보통신설비학회:학술대회논문집
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    • 한국정보통신설비학회 2004년도 하계학술대회
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    • pp.369-372
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    • 2004
  • In this paper, a low noise amplifier (LNA) in receiver of Low Noise Block Down Converter (LNB) for direct broadcasting service (DBS) is implemented by using GaAs HEMT The LNA is designed for operation between 10.7GHz-12.7GHz. The LNA consists of input, output matching circuits, DC-blocks and RF-chokes. The result of simulation of the LNA shows that a noise figure is less than 1.4dB and a gain is gloater than 9.2dB in the bandwidth of 10.7 to 12.7GHz with good flatness of 0. ldB

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2.5V 80dB 360MHz CMOS 가변이득 증폭기 (A 2.5V 80dB 360MHz CMOS Variable Gain Amplifier)

  • 권덕기;박종태;유종근
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.983-986
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    • 2003
  • This paper describes a 2.5V 80dB 360MHz CMOS VGA. A new variable degeneration resistor is proposed where the dc voltage drop over the degeneration resistor is minimized and employed in designing a low-voltage and high-speed CMOS VGA. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than 1.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$$\times$360${\mu}{\textrm}{m}$.

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