• Title/Summary/Keyword: DC-voltage

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A Study on a Rectenna for Low Power Density at 2.45 GHz (2.45 GHz대 저전력용 렉테나에 관한 연구)

  • Park, Bong-Kook;Seo, Hong-Eun;Cho, Ik-Hyun;Kim, Yea-Ji
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.9
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    • pp.862-867
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    • 2009
  • This paper presents a study on a rectenna for rectification of incident low power microwave signals with power densities less than 2 mW/$cm^2$ at 2.45 GHz. The proposed rectenna is designed and implemented by a rectifier with voltage doubler structure and a printed Yagi antenna which suppress re-radiation of the second order harmonic of fundamental frequency. The printed Yagi antenna has a gain of about 5 dB, and the measured conversion efficiencies of the rectenna are from 32 % to 42 % when its incident power levels are from 0 dBm to 14 dBm. The developed rectenna is expected to be useful in the power transmission system.

A 0.18-μm CMOS Low-Power and Wideband LNA Using LC BPF Loads (광대역 LC 대역 통과 필터를 부하로 가지는 0.18-μm CMOS 저전력/광대역 저잡음 증폭기 설계)

  • Shin, Sang-Woon;Seo, Yong-Ho;Kim, Chang-Wan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.1
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    • pp.76-80
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    • 2011
  • This paper has proposed a 3~5 GHz low-power and wideband LNA(Low Noise Amplifier), which has been implemented in a 0.18-${\mu}m$ CMOS technology. The proposed LNA has basically the noise-cancelling topology to achieve a balun-function, wideband input matching, and relative low noise figure. In addition, it has utilized a 2nd-order LC-band-pass filter(BPF) as its output load to achieve higher power gain and lower noise figure with the lowest dc power consumption among previously reported works. The proposed amplifier consumes only 3.94 mA from a 1.8 V supply voltage. The simulation results show a power gain of more than +17 dB, a noise figure of less than +4 dB, and an input IP3 of -15.5 dBm.

Dry Etching Characteristics of $YMnO_3$ Thin Films Using Inductively Coupled Plasma (유도결합 플라즈마를 이용한 $YMnO_3$ 박막의 건식 식각 특성 연구)

  • 민병준;김창일;창의구
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.2
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    • pp.93-98
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    • 2001
  • YMnO$_3$ films are excellent gate dielectric materials of ferroelectric random access memories (FRAMs) with MFSFET (metal -ferroelectric-semiconductor field effect transistor) structure because YMnO$_3$ films can be deposited directly on Si substrate and have a relatively low permittivity. Although the patterning of YMnO$_3$ thin films is the requisite for the fabrication of FRAMs, the etch mechanism of YMnO$_3$ thin films has not been reported. In this study, YMnO$_3$thin films were etched with Cl$_2$/Ar gas chemistries in inductively coupled plasma (ICP). The maximum etch rate of YMnO$_3$ film is 285$\AA$/min under Cl$_2$/(Cl$_2$+Ar) of 1.0, RF power of 600 W, dc-bias voltage of -200V, chamber pressure of 15 mTorr and substrate temperature of $25^{\circ}C$. The selectivities of YMnO$_3$ over CeO$_2$ and $Y_2$O$_3$ are 2.85, 1.72, respectively. The selectivities of YMnO$_3$ over PR and Pt are quite low. Chemical reaction in surface of the etched YMnO$_3$ thin films was investigated with X-ray photoelectron spectroscopy (XPS) surface of the selected YMnO$_3$ thin films was investigated with X-ray photoelectron spectroscopy(XPS) and secondary ion mass spectrometry (SIMS). The etch profile was also investigated by scaning electron microscopy(SEM)

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Dielectric Properties of Continuous Composition Spreaded $BaTiO_3-SrTiO_3$ Thin Films Prepared by Off-Axis RF Magnetron Sputtering System

  • Kim, Yoon-Hoe;Jung, Keun;Yoon, Seok-Jin;Park, Kyung-Bong;Choi, Ji-Won
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.326-326
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    • 2010
  • The dielectric properties of continuous composition spreaded (CCS) $BaTiO_3-SrTiO_3$ (BST) thin filmsgrown at room temperature and annealed at different temperature ($350^{\circ}C$ and $550^{\circ}C$) were investigated. Moreover, electrical properties (leakage current and breakdown voltage) of CCS BST thin films were also investigated. The aluminum top-electrode, sized by $200{\times}200\;{\mu}m2$ and apart from each other by $300\;{\mu}m$, were deposited on the CCS BST thin films by the DC sputtering system. The dielectric properties of the CCS BST thin films were significantly influenced depending on the distance from $BaTiO_3$ and $SrTiO_3$ targets which was attributed to the $BaTiO_3-SrTiO_3$ composition ratio. The maps of dielectric constants and loss tangents were plotted via $1500\;{\mu}m$ - step measuring. The specific points showing the dielectric constant (k: ~300) and loss tangent (tand: ~0.008) at 1 MHz were found.

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Fabrications and Properties of Al/$VF_2$/$n^+$-Si(100) Structures by Dip Coating Methode (Dip Coating 법에 의한 Al/$VF_2$-TrFE/Si(100) 구조의 제작 특성)

  • Kim, Ka-Lam;Jeong, Sang-Hyun;Yun, Hyeong-Seon;Lee, Woo-Seok;Kwak, No-Won;Kim, Kwang-Ho
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.20-21
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    • 2008
  • Ferroelectric vinylidene fluoride-trifluoroethylene ($VF_2$-TrFE) copolymer films were directly deposited on degenerated Si ($n^+$, 0.002 $\Omega{\cdot}cm$) using by dip coating method. A 1 ~ 3 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene ($VF_2$:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers using dip coating method for 10 seconds. After Post-Annealing in a vacuum ambient at 100~200 $^{\circ}C$ for 60 min, upper aluminum electrodes were deposited by thermal evaporation through the shadow mask to complete the MFS structure. The ferroelectric $\beta$-phase peak of films, depending on the annealing temperature, started to show up around $125^{\circ}C$, and the intensity of the peak increased with increasing annealing temperature. Above $175^{\circ}C$, the peak started to decrease. The C-V characteristics were measured using a Precision LCR meter (HP 4284A) with frequency of 1MHz and a signal amplitude of 20 mV. The leakage-current versus electric-field characteristics was measured by mean of a pA meter/DC voltage source (HP 4140B).

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LC Orientation Characteristics of NLC on Polyimide Surface According to Ion-beam Irradiation Angles (이온빔 조사각도에 따른 네마틱 액정의 액정 배향 특성)

  • Lee, Kang-Min;Oh, Byeong-Yun;Park, Hong-Gyu;Lim, Ji-Hun;Lee, Won-Kyu;Na, Hyun-Jae;Kim, Byoung-Yong;Han, Jeong-Min;Lee, Sang-Keuk;Seo, Dae-Shik
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.329-329
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    • 2008
  • To date, rubbing has been widely used to align LC molecules uniformly. Although rubbing can be simple, it has fundamental problems such as the generation of defects by dust and static electricity, and difficulty in achieving a uniform LC alignment on a large substrate. Therefore, noncontact alignment has been investigated. Ion beam induced alignment method, which provides controllability, nonstop process, and high resolution display. In this study, we investigated liquid crystal (LC) alignment with ion beam (IB) that non contact alignment technique on polyimide and electro-optical characteristics of twisted nematic (TN)-liquid crystal display (LCD) on the poly imide under various ion beam angles. In this experiment, Polyimide layer was coated on glass by spin-coating and Voltage-transmittance(VT) and response time characteristics of the TN cell were measured by a LCD evaluation system. The good characteristics of the nematic liquid crystal (NLC) alignment with the ion beam exposure poly imide surface was observed. The tilt angle of NLC on the PI surface with ion beam exposure can be measured under $1^{\circ}4 for all of irradiation angles. In addition, it can be achieved the good ED properties, and residual DC property of the ion beam aligned TN cell on polyimide surface.

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High-Speed Digital/Analog NDR ICs Based on InP RTD/HBT Technology

  • Kim, Cheol-Ho;Jeong, Yong-Sik;Kim, Tae-Ho;Choi, Sun-Kyu;Yang, Kyoung-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.3
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    • pp.154-161
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    • 2006
  • This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

Analysis of Distortion Characteristic of Amplitude Modulated Signal through a Current-Mode-Logic Frequency Divider (전류모드논리 주파수 분할기를 통한 기저대역 AM 변조 신호의 왜곡 특성 연구)

  • Kim, Hyeok;Park, Youngcheol
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.7
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    • pp.620-624
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    • 2016
  • In this paper we designed a current mode logic frequency divider to transmit a baseband amplitude modulated signal. From simulation result, we studied input and output waveforms according to the variation of input bias voltage. For the purpose of the verification of the study, we designed a current mode logic frequency divider at 1,400 MHz. The designed frequency divider operates between 100 MHz and 3,000 MHz, for -33 dBm input power. The circuit draws $I_{total}=30mA$ from $V_{DD}=3V$ supply, and the simulation result shows that an amplitude modulated signal at 1,400 MHz with the modulation index of 0.5 was successfully downconverted to 700 MHz.

Characteristics of Nano Particle Precipitation and Residual Ozone Decomposition for Two-Stage ESP with DBD (배리어 유전체 방전형 2단 전기집진기의 나노입자 집진 및 잔류 오존 제거 특성)

  • Byeon, Jeong-Hoon;Ji, Jun-Ho;Yoon, Ki-Young;Hwang, Jung-Ho
    • Proceedings of the KSME Conference
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    • 2003.04a
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    • pp.1678-1683
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    • 2003
  • DBD(Dielectric Barrier Discharge) plasma in air is well established for the production of large quantities of ozone and is more recently being applied to aftertreatment processes for HAPs(Hazardous Air Pollutants). Although DBD high electron density and energy, its potential use as nano and sub-micron sized particle charging are not well known. Aim of this work is to determine design and operating parameters of a two-stage ESP with DBD. DBD and ESP are used as particle charger and precipitator, respectively. We measured particle precipitation efficiency of two-stage ESP and estimated ozone decomposition of both pelletized $MnO_2$ catalyst and pelletized activated carbon. To examine the particle precipitation efficiency, nano and sub-micron sized particles were generated by a tube furnace and an atomizer. AC voltage of $7{\sim}10$ kV(rms) and 60 Hz is used as DBD plasma source. DC -8 kV is applied to the ESP for particle precipitation. The overall particle collection efficiency for the two-stage ESP with DBD is over 85 % under 0.64 m/s face velocity. Ozone decomposition efficiency with pelletized $MnO_2$ catalyst or pelletized activated carbon packed bed is over 90 % when the face velocity is under 0.4 m/s in dry air.

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Linearity Enhancement of Partially Doped Channel GaAs-based Double Heterostructure Power FETs (부분 채널도핑된 GaAs계 이중이종접합 전력FET의 선형성 증가)

  • Kim, U-Seok;Kim, Sang-Seop;Jeong, Yun-Ha
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.1
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    • pp.83-88
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    • 2002
  • To increase the device linearities and the breakdown-voltages of FETs, $Al_{0.25}$G $a_{0.75}$As/I $n_{0.25}$G $a_{0.75}$As/A $l_{0.25}$G $a_{0.75}$As partially doped channel FET(DCFET) structures are proposed. The metal insulator-semiconductor(MIS) like structures show the high gate-drain breakdown voltage(-20V) and high linearities. We propose a partially doped channel structure to enhance the device linearity to the homogeneously doped channel structure. The physics of partially doped channel structure is investigated with 2D device simulation. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range. bias range.