• Progress in Superconductivity and Cryogenics
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• v.23 no.4
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• pp.19-24
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• 2021

The low normal zone propagation velocity (NZPV) of high-temperature superconducting (HTS) tape leads to a quench protection problem in HTS magnet applications. To overcome this limitation, various studies were conducted on HTS coils without turn-to-turn insulation (NI coils) that can achieve self-protection. On the other hand, NI coils have some disadvantages such as slow charging and discharging time. Previously, the HTS coils with turn-to-turn insulation (INS coils) were operated in power supply (PS) driven mode, which requires physical contact with the external PS at room-temperature, not in persistent current mode. When a quench occurs in INS coils, the low NZPV delays quench detection and protection, thereby damaging the coils. However, the rotary HTS flux pump supplies the DC voltage to the superconducting circuit with INS coils in a non-contact manner, which causes the INS coils to operate in a persistent current mode, while enabling quench protection. In this paper, a new protection characteristic of HTS coils is investigated with INS coils charging through the rotary HTS flux pump. To experimentally verify the quench protection characteristic of the INS coil, we investigated the current magnitude of the superconducting circuit through a quench, which was intentionally generated by thermal disturbances in the INS coil under charging or steady state. Our results confirmed the protection characteristic of INS coils using a rotary HTS flux pump.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Korean Vacuum Society
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• v.16 no.6
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• pp.483-488
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• 2007

Current feeder system (CFS) for Korea superconducting tokamak advanced research(KSTAR) project plays a role to interconnect magnet power supply (MPS) and superconducting (SC) magnets through the normal bus-bar at the room temperature(300 K) environment and the SC bus-line at the low temperature (4.5 K) environment. It is divided by two systems, i.e., toroidal field system which operates at 35 kA DC currents and poloidal field system wherein 20$\sim$26 kA pulsed currents are applied during 350 s transient time. Aside from the vacuum system of main cryostat, an independent vacuum system was constructed for the CFS in which a roughing system is consisted by a rotary and a mechanical booster pump and a high vacuum system is developed by four cryo-pumps with one dry pump as a backing pump. A self interlock and its control system, and a supervisory interlock and its control system are also established for the operational reliability as well. The entire CFS was completely tested including the reliability of local/supervisory control/interlock, helium gas leakage, vacuum pressure, and so on.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.318-330
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• 2009

A high heat flux test facility using a graphite heating panel was constructed and is presently in operation at Korea Atomic Energy Research Institute, which is called KoHLT-1. Its major purpose is to carry out a thermal cycle test to verify the integrity of a HIP (hot isostatic pressing) bonded Be mockups which were fabricated for developing HIP joining technology to bond different metals, i.e., Be-to-CuCrZr and CuCrZr-to-SS316L, for the ITER (International Thermonuclear Experimental Reactor) first wall. The KoHLT-1 consists of a graphite heating panel, a box-type test chamber with water-cooling jackets, an electrical DC power supply, a water-cooling system, an evacuation system, an He gas system, and some diagnostics, which are equipped in an authorized laboratory with a special ventilation system for the Be treatment. The graphite heater is placed between two mockups, and the gap distance between the heater and the mockup is adjusted to $2{\sim}3\;mm$. We designed and fabricated several graphite heating panels to have various heating areas depending on the tested mockups, and to have the electrical resistances of $0.2{\sim}0.5$ ohms during high temperature operation. The heater is connected to an electrical DC power supply of 100 V/400 A. The heat flux is easily controlled by the pre-programmed control system which consists of a personal computer and a multi function module. The heat fluxes on the two mockups are deduced from the flow rate and the coolant inlet/out temperatures by a calorimetric method. We have carried out the thermal cycle tests of various Be mockups, and the reliability of the KoHLT-1 for long time operation at a high heat flux was verified, and its broad applicability is promising.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.252-252
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• 2016

최근 학계나 산업계에서 indium tin oxide (ITO)의 높은 전기 전도도 및 광투과율을 이용하여 줄 발열을 기초로 하는 투명 면상 발열체에 대한 연구가 활발히 진행 되고 있다. 하지만 단일 ITO 박막으로 제작한 투명 면상 발열체는 온도가 상승함에 따라 균일하게 발열 되지 않으며, 글라스의 곡면 부분에서 유연성이 부족하여 크랙이 발생하는 다양한 문제점들을 가지고 있다. 이를 해결하기 위해 ITO의 결정화 온도 $160^{\circ}C$ 이상의 고온공정 또는 증착 후 열처리가 필요 하는 추가적인 공정이 필요하다. 따라서 본 연구에서는 단일 ITO 박막의 단점을 개선하는 ITO/Ag/ITO 하이브리드 구조의 투명 면상 발열체를 제작하여 전기적, 광학적 특성을 비교하고 발열량, 온도 균일성, 발열 유지 안정도를 조사하였다. 본 연구에서는 $50{\times}50mm$ 크기의 non-alkali glass (Corning E-2000) 기판 상에 마그네트론 스퍼터링 공정으로 상온에서 ITO/Ag/ITO 박막을 연속적으로 증착 하여 다층구조의 하이브리드 형 투명 면상 발열체를 제조하였다. 박막 증착 파워는 DC (Ag) power 100 W, RF (ITO) power 200 W로 하였으며 ITO박막두께는 40 nm로 고정 시키고 Ag박막 두께는 10 ~ 20 nm로 변화를 주었다. 증착원은 3인치 ITO 단일 타깃(SnO2, 10 wt.%)과 Ag 금속 타깃 (순도 99.99%)을 사용하였으며, 고순도 Ar을 이용하여 방전하였으며 총 주입량은 20 sccm, working pressure는 1.0 Pa을 유지하였다. 증착전 타깃 표면의 불순물 제거와 방전의 안정성을 유지하기 위해 10분간 pre-sputtering을 진행하고 증착하였다. 증착한 박막의 전기적, 광학적 특성은 각각 Hall-effect measurements system (ECOPIA, HMS3000), UV-Vis spectrophotometer (UV-1800, SHIMADZU)으로 측정하였으며, 하이브리드 표면의 구조 및 형상은 field emission-scanning electron microscopy (FE-SEM, Hitachi S-4800)으로 관찰하였다. 또한 투명 면상 발열체의 성능은 0.5 ~ 3 V/cm의 다양한 전압을 power supply (Keithly 2400, USA)를 통해서 시편 양 끝단에 인가한 후 시간에 따른 투명면상 발열체의 표면 온도변화를 infrared thermal imager (IR camera, Nikon)를 이용하여 관찰하였다. 하이브리드 구조를 가진 ITO박막의 두께는 40 nm로 고정 시키고 Ag박막의 두께는 10, 15, 20 nm로 변화를 주었다. 이들 박막의 면저항 값은 각각 5.3, 3.2, $2.1{\Omega}/{\Box}$였으며, 투과도는 각각 86.9, 81.7, 66.5 %였다. 이에 비해 두께 95 nm의 단일 ITO박막의 면저항 값은 $59.5{\Omega}/{\Box}$였으며, 투과도는 89.1 %였다. 하이브리드 구조의 전기적특성은 금속층의 두께가 증가할수록 캐리어 농도 값이 증가함에 따라 비저항 값이 감소되어 면저항 값도 감소된 것이며, 금속 삽입층의 전도특성이 비저항에 큰 영향을 주고 있음을 보여준다. 하지만 금속 층의 두께가 증가할수록 Ag층이 연속적인 막을 형성하여 반사율이 증가함에 따라 투과도가 감소하였다. 따라서 하이브리드 구조를 가진 투명 면상 발열체에 금속 삽입층의 두께 조절은 매우 중요한 인자임을 확인 할 수 있었다. 또한 발열성능을 평가 하기 위해 시편 양 끝단에 3 V전압을 인가한 결과, 금속 삽입층의 두께가 10 nm에서 5 nm씩 증가한 하이브리드 구조를 가진 투명면상 발열체의 최고 온도는 각각 98, 150, $167^{\circ}C$ 였으며, 단일 ITO의 최고 온도는 $32^{\circ}C$였다. 이 것은 동일한 두께 (95 nm)의 단일 ITO 박막과 비교하여 면저항이 낮은 하이브리드 박막의 발열량은 약 $120^{\circ}C$로 발열효율이 매우 우수한 것을 확인 할 수 있었다.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.34 no.1
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• pp.27-34
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• 2010

In a test duct with closed configuration, particle removal performance of an edge-plate type electrostatic precipitator (ESP) was evaluated at a high flow rate in $CO_2$ rich environments by changing gap distances between collection plates, concentrations of $CO_2$, particle sizes, types of electrodes, and types of power supplies. At the same experimental conditions, collection efficiency of particles with the mean particle size, 300 nm, decreased as the gap distance and $CO_2$ concentration increased because of low electrostatic force and low discharged current. In addition, as the particle size increased, the efficiency increased because of high charging rate of the large particles. With the electrode type which has higher surface area of a discharging plate and with the power supply which applied 25 kHz-pulsed DC voltages, the removal efficiency was high even in rich $CO_2$ condition due to high electrostatic force at the same power consumption.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Applied Chemistry for Engineering
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• v.9 no.7
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• pp.1030-1035
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• 1998

The porous alumina membrane was prepared from aluminum metal(99.8%) by anodic oxidation using DC power supply of constant current mode in an aqueous solution of sulfuric acid. To prevent the chemical dissolution of alumina membrane, $Al_2(SO_4)_3$, $AlPO_4$ and $Al(NO_3)_3$ which could be considered to supply $Al^{3+}$ ions were added to electrolyte solution at a reaction temperature of $20^{\circ}C$ and cumulative charge of $150C/cm^2$. Effects of these additives on the formation of porous alumina membrane were evaluated under various electrolyte concentration(5~20 wt%) and current densities($10{\sim}50mA/cm^2$). The membrane surfaces which were prepared in electrolyte solution with all the additives except $Al_2(SO_4)_3$ were damaged. However, when $Al_2(SO_4)_3$ was added to the $H_2SO_4$ solution, an uniform surface of porous alumina was obtained. Also, it was shown that the pore size of membrane was nearly independent on the quantity of $Al_2(SO_4)_3$ added at same electrolyte concentration and current density.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.