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Strain-Relaxed SiGe Layer on Si Formed by PIII&D Technology

  • Han, Seung Hee;Kim, Kyunghun;Kim, Sung Min;Jang, Jinhyeok
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.155.2-155.2
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    • 2013
  • Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

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A 1.1V 12b 100MS/s 0.43㎟ ADC based on a low-voltage gain-boosting amplifier in a 45nm CMOS technology (45nm CMOS 공정기술에 최적화된 저전압용 이득-부스팅 증폭기 기반의 1.1V 12b 100MS/s 0.43㎟ ADC)

  • An, Tai-Ji;Park, Jun-Sang;Roh, Ji-Hyun;Lee, Mun-Kyo;Nah, Sun-Phil;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.122-130
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    • 2013
  • This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

Precalcification Treatment of $TiO_2$ Nanotube on Ti-6Al-4V Alloy (Ti-6Al-4V 합금 표면에 생성된 $TiO_2$ 나노튜브의 전석회화 처리)

  • Kim, Si-Jung;Park, Ji-Man;Bae, Tae-Sung;Park, Eun-Jin
    • The Journal of Korean Academy of Prosthodontics
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    • v.47 no.1
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    • pp.39-45
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    • 2009
  • Statement of problem: Recently precalcification treatment has been studied to shorten the period of the implant. Purpose: This study was performed to evaluate the effect of precalcification treatment of $TiO_2$ Nanotube formed on Ti-6Al-4V Alloy. Material and methods: Specimens of $20{\times}10{\times}2\;mm$ in dimensions were polished sequentially from #220 to #1000 SiC paper, ultrasonically washed with acetone and distilled water for 5 min, and dried in an oven at $50^{\circ}C$ for 24 hours. The nanotubular layer was processed by electrochemical anodic oxidation in electrolytes containing 0.5 M $Na_2SO_4$ and 1.0 wt% NaF. Anodization was carried out using a regulated DC power supply (Kwangduck FA, Korea) at a potential of 20 V and current density of $30\;㎃/cm_2$ for 2 hours. Specimens were heat-treated at $600^{\circ}C$ for 2 hours to crystallize the amorphous $TiO_2$ nanotubes, and precalcified by soaking in $Na_2HPO_4$ solution for 24 hours and then in saturated $Ca(OH)_2$ solution for 5 hours. To evaluate the bioactivity of the precalcified $TiO_2$ nanotube layer, hydroxyapatite formation was investigated in a Hanks' balanced salts solution with pH 7.4 at $36.5^{\circ}C$ for 2 weeks. Results: Vertically oriented amorphous $TiO_2$ nanotubes of diameters 48.0 - 65.0 ㎚ were fabricated by anodizing treatment at 20 V for 2 hours in an 0.5 M $Na_2SO_4$ and 1.0 NaF solution. $TiO_2$ nanotubes were composed with strong anatase peak with presence of rutile peak after heat treatment at $600^{\circ}C$. The surface reactivity of $TiO_2$ nanotubes in SBF solution was enhanced by precalcification treatment in 0.5 M $Na_2HPO_4$ solution for 24 hours and then in saturated $Ca(OH)_2$ solution for 5 hours. The immersion in Hank's solution for 2 weeks showed that the intensity of $TiO_2$ rutile peak increased but the surface reactivity decreased by heat treatment at $600^{\circ}C$. Conclusion: This study shows that the precalcified treatment of $TiO_2$ Nanotube formed on Ti-6Al-4V Alloy enhances the surface reactivity.

An Experiment and Analysis for Standardize Measurement on CCFL (냉음극 형광램프의 표준화 계측을 위한 실험과 분석)

  • Jin, Dong-Jun;Jeong, Jong-Mun;Jeong, Hee-Suk;Kim, Jin-Shon;Lee, Min-Kyu;Kim, Jung-Hyun;Koo, Je-Huan;Gwon, Gi-Cheong;Kang, June-Gill;Choi, Eun-Ha;Cho, Guang-Sup
    • Journal of the Korean Vacuum Society
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    • v.17 no.4
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    • pp.331-340
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    • 2008
  • A method of measuring the current and voltage is suggested in the circuit of cold cathode fluorescent lamps (CCFLs) which are driven at a high frequency of $50{\sim}100\;kHz$ and a high voltage of several kV. It is difficult to measure the current and voltage in the lamp circuit, because the impedance of the probe at high voltage side causes the leakage current and the variation of luminance. According to the analysis of equivalence circuit with the probe impedance and leakage current, the proper measuring method is to adjust the input DC voltage and to keep the specific luminance when the probe is installed at a high voltage circuit. The lamp current is detected with a current probe or a high frequency current meter at the ground side and the voltage is measured with a high voltage probe at the high voltage side of lamp. The lamp voltage($V_C$) is measured between the ballast capacitor and the lamp electrode, and the output voltage($V_I$) of inverter is measured between inverter output and ballast capacitor. As the phases of lamp voltage($V_C$) and current ($I_G$) are nearly the same values, the real power of lamp is the product of the lamp voltage($V_C$) by the lamp current($I_G$). The measured value of the phase difference between inverter output voltage($V_I$) and lamp current($I_G$) is appreciably deviated from the calculated value at $cos{\theta}=V_C/V_I$.

A 13b 100MS/s 0.70㎟ 45nm CMOS ADC for IF-Domain Signal Processing Systems (IF 대역 신호처리 시스템 응용을 위한 13비트 100MS/s 0.70㎟ 45nm CMOS ADC)

  • Park, Jun-Sang;An, Tai-Ji;Ahn, Gil-Cho;Lee, Mun-Kyo;Go, Min-Ho;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.3
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    • pp.46-55
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    • 2016
  • This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

Effects of Photoperiod and Light Intensity on the Growth and Glucosinolates Content of Three Brassicaceae Species in a Plant Factory (식물공장에서 광주기 및 광강도가 십자화과 3종의 생육과 글루코시놀레이트 함량에 미치는 영향)

  • Kim, Sunwoo;Bok, Gwonjeong;Shin, Juhyung;Park, Jongseok
    • Journal of Bio-Environment Control
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    • v.31 no.4
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    • pp.416-422
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    • 2022
  • This study was conducted to investigate the effect of each light intensity and photoperiod combination on the growth and glucosinolates (GSLs) content of three species of Brassicaceae plants under the same daily light integral (DLI) conditions. Seeds of leaf mustard (Brassica juncea (L.) Czern.), red mustard(Brassica juncea L.) and kale (Brassica oleracea L. var. acephala (DC.) Alef.) were sown in a rockwool cubes and grown for three weeks. DLI was set to 10 mol·m-2·d-1 and treated with 10h-280, 14h-200, 18h-155, 22h-127 µmol·m-2·s-1 for three weeks. As a result at 14h-200 µmol·m-2·s-1 treatment, shoot fresh/dry weight, the number of leaves, and leaf area were increased in leaf mustard and kale but there was no significant difference in other treatments. In the total GSLs content, the treatment of 14h-200 µmol·m-2·s-1 increased significantly 139.95, 135.87, 154.03% compared to 10h-280, 18h-155, 22h-127 µmol·m-2·s-1 treatment in red mustard, and 14h-200 µmol·m-2·s-1 treatment increased significantly 132.96, 132.96, 134.03% compared to other treatments in kale. In red mustard, the treatment of 18h-155 µmol·m-2·s-1 showed an increase in shoot fresh/dry weight and the total GSLs contents than other photoperiods and 14h-200 µmol·m-2·s-1 treatment, the number of leaves significantly 15.62, 12.12, and 32.14% higher than other photoperiods. Since the DLI response is different depending on species even for similar Brassicaceae crops, it is necessary to get more detailed results by conducting optical light quality studies and deriving optimal DLI conditions to achieve minimum power consumption and maximum efficiency.

Electromagnetic Modeling of High Altitude Electromagnetic Pulse Coupling into Large-Scale Underground Multilayer Structures (다층 지하 구조물로의 고고도 전자기파(HEMP) 커플링 현상에 대한 전자기적 모델링)

  • Kang, Hee-Do;Oh, Il-Young;Kim, Jung-Ho;Yook, Jong-Gwan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.3
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    • pp.392-401
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    • 2012
  • This paper gives a electromagnetic coupling mechanism of the high altitude electromagnetic pulse (HEMP) into large- scale underground multilayer structures using analytic and numerical methods. The modeling methods are firstly addressed to the HEMP source which can be generated by intentional nuclear explosion. The instantaneous and intense electromagnetic pulse of the HEMP source is concerned from DC to 100 MHz band, because the power spectrum of the HEMP is rapidly decreased under -30 dB over the 100 MHz band. Through this range, a penetrated electric field distribution is computed within the large-scale underground multilayer structures. As a result, the penetrated electric field intensities at 0.1 and 1 MHz are about 10 and 5 kV/m, respectively. Therefore, additional shielding techniques are introduced to protect buried structures within the large-scale underground structures such as high-lossy material and filtering structures (wire screen).

A Low-pass filter design for suppressing the harmonics of 2.4GHz RFID tag (2.4GHz RFID 태그용 고조파 억제를 위한 저역통과필터의 설계)

  • Cho, Young Bin;Kim, Byung-Soo;Kim, Jang-Kwon
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.3
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    • pp.59-64
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    • 2002
  • In the RFID system using ISM-band, The tag mounted at the object has used the DC power by rectifying the RF signals of the small antenna for operating the micro-controller and memory. The performance of the tag would be reduced because of the second harmonics generated by the nonlinearity of the semiconductor and the spurious signal excited the high order mode of the antenna. This paper has realized the novel type low-pass filter with "the Stub-I type DGS slot structure" to improve the efficiency of the tag by suppressing the harmonics. The optimized frequency character at the pass-band/stop-band has obtained by tuning the stub width and slit width of I type slot. The measured result of the LPF has the cutoff frequency 3.25 GHz, the insertion loss about -0.29~-0.3 dB at pass-band 2.4 GHz~2.5 GHz, the return loss about -27.688~-33.665 dB at pass-band with a good performance, and the suppression character is about -19.367 dB at second harmonics frequency 4.9 GHz. This DGS LPF may be applied the various application as the RFID, WLAN to improve the efficiency of the system by suppressing the harmonics and spurious signals. 

A Study on PWM Speed Controller for Long line Fishing Motor (어로 작업용 연승기 전동기의 PWM 속도제어기에 관한 연구)

  • Vuong, Duc-Phuc;Bae, Cherl-O;Ahn, Byong-Won
    • Journal of the Korean Society of Marine Environment & Safety
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    • v.21 no.1
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    • pp.97-102
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    • 2015
  • The long line fishing machine is combined with motor and two disc rollers has used on the small size fishing-boat under 1 ton located in near Jeollanam-do seaside. The long line fishing motor is controlled only one direction because the fishing line is loaded heavily at pulling up. On this paper we made the long line fishing 400W power motor controller which it was usually applied under 1 ton fishing boat, and designed the controller using PWM chip, Half bridge driver and MOSFET for one direction motor control. Furthermore some user convenience devices were added like battery indicator and safety protection circuit for battery overdischarge and battery source wire mismatch connection. So we protected the battery from overdicharging when the battery voltage was below 11.5V and fishermen didn't need to worry about source lines misconnection anymore. We confirmed the test version of controller was the good working condition at land and sea.

Low Conversion Loss 94 GHz MHEMT MIMIC Resistive Mixer (낮은 변환손실 특성의 94 GHz MHEMT MIMIC Resistive 믹서)

  • An Dan;Lee Bok-Hyung;Lim Byeong-Ok;Lee Mun-Kyo;Oh Jung-Hun;Baek Yong-Hyun;Kim Sung-Chan;Park Jung-Dong;Shin Dong-Hoon;Park Hyung-Moo;Park Hyun-Chang;Kim Sam-Dong;Rhee Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.5 s.335
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    • pp.61-68
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    • 2005
  • In this paper, low conversion loss 94 GHz MIMIC resistive mixer was designed and fabricated. The $0.1{\mu}m$ InGaAs/InAlAs/GaAs Metamorphic HEMT, which is applicable to MIMIC's, was fabricated. The DC characteristics of MHEMT are 665 mA/mm of drain current density, 691 mS/mm of maximum transconductance. The current gain cut-off frequency(fT) is 189 GHz and the maximum oscillation frequency(fmax) is 334 GHz. A 94 GHz resistive mixer was fabricated using $0.1{\mu}m$ MHEMT MIMIC process. From the measurement, the conversion loss of the 94 GHz resistive mixer was 8.2 dB at an LO power of 10 dBm. P1 dB(1 dB compression point) of input and output were 9 dBm and 0 dBm, respectively. LO-RF isolations of resistive mixer was obtained 15.6 dB at 94.03 GHz. We obtained in this study a lower conversion loss compared to some other resistive mixers in W-band frequencies.