• 한국인터넷방송통신학회논문지
• /
• 제21권4호
• /
• pp.135-141
• /
• 2021

산업자동화에 적합한 구형파 구동 BLDC 영구자석 전동기 설계 및 개발, 위치검출방식 회로와 드라이버 개발에 관심이 증가하고 있다. 그러나 이 전동기는 스위칭 손실에 의한 효율 저하 및 진동, 소음 등으로 인하여 가격적·기능적인 장점에도 불구하고 그 응용에 있어서는 다소 제한적인 실정이다. BLDC 모터를 설계하고 조립하는 과정에 있어 자기회로 설계의 문제 또는 조립과정상의 제품 불 균일 등으로 인하여 자극 각이 균일하지 않거나 자속분포가 왜현되는 문제가 발생하는데, 이러한 것들이 위치검출 어긋남의 원인이 되어 모터 특성을 악화시킨다. 또한 위치센서로부터 발생된 신호가 정확히 드라이버로 피드백 되어야만 정현파 구동 BLDC 시스템이 안정적으로 동작할 수 있다. 그러나 발생된 신호가 외부의 영향인 자속밀도 편차나 착자 기술에 의해 DC offset 성분이 발생하여 안정적인 위치검출을 할 수 없기에 본 연구에서는 DC offset 성분을 제거할 수 있는 제안된 회로를 연구하고자 한다.

• 조명전기설비학회논문지
• /
• 제30권1호
• /
• pp.28-37
• /
• 2016

Fault locating is an important element to minimize the damage of power system. The computation error of fault locator may occur by the influence of the DC offset component during phasor extraction. In order to minimize the bad effects of DC offset component, this paper presents an improved fault location algorithm based on a DC offset removal filter for short fault in a double circuit transmission line. We have modeled a 154kV double circuit transmission line by the ATP software to demonstrate the effectiveness of the proposed fault locating algorithm. The line to line short faults were simulated and then collected simulation data was used. It can be seen that the error rate of fault locating estimation by the proposed algorithm decreases than the error rate of fault locating estimation by conventional algorithm.

• 전기학회논문지
• /
• 제59권8호
• /
• pp.1360-1365
• /
• 2010

In this paper, we propose a distance relaying algorithm using a Discrete Fourier Transform (DFT)-based modified phasor estimation method to eliminate the adverse influence of exponentially decaying DC offsets. Most distance relays are based on estimating phasors of the voltage and current signals. A DFT is generally used to calculate the phasor of the fundamental frequency component in digital protective relays. However, the output of the DFT contains an error due to exponentially decaying DC offsets. For this reason, distance relays have a tendency to over-reach or under-reach in the presence of DC offset components in a fault current. Therefore, the decaying DC components should be taken into consideration when calculating the phasor of the fundamental frequency component of a relaying signal. The error due to DC offsets in a DFT is calculated and eliminated using the outputs of an even-sample-set DFT and an odd-sample-set DFT, so that the phasor of the fundamental component can be accurately estimated. The performance of the proposed algorithm is evaluated for a-phase to ground faults on a 345 kV, 50 km, simple overhead transmission line. The Electromagnetic Transient Program (EMTP) is used to generate fault signals. The evaluation results indicate that adopting the proposed algorithm in distance relays can effectively suppress the adverse influence of DC offsets.

• Journal of Power Electronics
• /
• 제15권6호
• /
• pp.1593-1600
• /
• 2015

This paper proposes a novel compensation algorithm of current offset error for single-phase linear compressor in home appliances. In a half-bridge inverter, current offset error may cause unbalanced DC-link voltage when the DC-link is comprised of two serially connected capacitors. To compensate the current measurement error, the synchronous reference frame transformation is used for detecting the measurement error. When an offset error occurs in the output current of the half-bridge inverter, the d-axis current has a ripple with frequency equal to the fundamental frequency. With the use of a proportional-resonant controller, the ripple component can be removed, and offset error can be compensated. The proposed compensation method can easily be implemented without much computation and additional hardware circuit. The validity of the proposed algorithm is verified through experimental results.

• 전기학회논문지
• /
• 제57권9호
• /
• pp.1485-1490
• /
• 2008

This paper proposes a new Fourier transform-based phasor estimation method to eliminate the adverse influence of the exponentially decaying dc offsets when Discrete Fourier Transform (DFT) is used to calculate the phasor of the fundamental frequency component in a relaying signal. By subtracting the result of odd-sample-set DFT from the result of even-sample-set DFT, the information of dc offsets can be obtained. Two dc offsets in a relaying signal are treated as one dc offset which is piecewise approximated in one cycle data window. The effect of the dc offsets can be eliminated by the approximated dc offset. The performance of the proposed algorithm is evaluated by using computer-simulated signals and EMTP-generated signals. The algorithm is also tested on a hardware board with TMS320C32 microprocessor. The evaluation results indicate that the proposed algorithm has the stable and accurate eliminating performance even if the input signal contains two decaying dc components having different time constants.

• 조명전기설비학회논문지
• /
• 제28권11호
• /
• pp.68-76
• /
• 2014

This paper presents an offset error compensation algorithm for the accurate phase angle of the grid voltage in single-phase grid-connected inverters. The offset error generated from the grid voltage measurement process cause the fundamental harmonic component with grid frequency in the synchronous reference frame phase lock loop (PLL). As a result, the grid angle is distorted and the power quality in power systems is degraded. In addition, the dq-axis currents in the synchronous reference frame and phase current have the dc component, first and second order ripples compared with the grid frequency under the distorted grid angle. In this paper, the effects of the offset and scaling errors are analyzed based on the synchronous reference frame PLL. Particularly, the offset error can be estimated from the integrator output of the synchronous reference frame PLL and compensated by using proportional-integral controller. Moreover, the RMS (Root Mean Square) function is proposed to detect the offset error component. The effectiveness of the proposed algorithm is verified through simulation and experiment results.

• 전기학회논문지
• /
• 제65권6호
• /
• pp.1108-1114
• /
• 2016

The cause of failure in the AT feeding system is divided into grounding, short-circuit of feeding circuit and internal faults of the railway substation. Since the fault current is very high, real-time current is detected and the failure must be immediately removed. In this paper, a new DC offset elimination filter that can remove component to decrease in the form of exponential function using low-pass filter was proposed in order to extract the fundamental wave from distorted fault current. In order to confirm the performance of the proposed filter method, AT feeder system was modelled by simulation tool and simulations were performed under various conditions such as fault location, fault resistance and fault voltage phase angle in case of trolley-rail short-circuit fault. When applying the proposed DC-offset removal method, it can be seen that the phase delay and gain error did not appear.

• KIEE International Transactions on Power Engineering
• /
• 제5A권2호
• /
• pp.138-143
• /
• 2005

During faults, the voltage and current signals available to the relay are affected by the decaying dc component and harmonics. In order to make appropriate and accurate decisions, most of the relaying algorithms require the fundamental frequency phasor information that is immune to decaying dc effect and harmonics. The conventional Fourier ph as or estimation algorithm is affected by the presence of decaying-exponential transients in the fault signal. This paper presents a modified Fourier algorithm, which effectively eliminates the decaying dc component and the harmonics present in the fault signal. The decaying dc parameters are estimated by means of an out-of-band filtering technique. The decaying dc offset and harmonics are removed by means of a simple computational procedure that involves the design of two sets of Orthogonal digital OFT filters tuned at different frequencies and by creating three off-line look-up tables. The technique was tested for different decay rates of the decaying dc component. It was also compared with the conventional mimic plus the full cycle OFT algorithm. The results indicate that the proposed technique has a faster convergence to the desired value compared to the conventional mimic plus OFT algorithms over a wide range of decay rates. In all cases, the convergence to the desired value was achieved within one cycle of the power system frequency.

• 전기학회논문지P
• /
• 제64권4호
• /
• pp.291-296
• /
• 2015

Transmission line is exposed to a large area, and then faults are likely to occur than the other component of power system. When a fault occurs on a transmission line, fault locator helps fast recovery of power supply on power system. This paper deals with the design of a digital fault locator for improvement accuracy of the fault distance estimation and a fault occurrence position for transmission line. The algorithm of a fault locator uses a DC offset removal filter and DFT filter. The algorithm utilizes a fault data of GPS time synchronized. The computed fault information is transmitted to the other side substation through communication. The digital fault locator includes MPU module, ADPU module, SIU module, and a power module. The MMI firmware and software of the fault locator was implemented.

• Journal of Power Electronics
• /
• 제14권2호
• /
• pp.383-391
• /
• 2014

For the digital control of systems such as grid-connected inverters, measuring inverter output currents accurately is essential. However, current measurement offsets are inevitably generated by current measurement paths and cause DC current components in real inverter output currents. Real inverter output currents with DC components cause the DC-link capacitor voltage to oscillate at the frequency of a utility voltage. For these reasons, current measurement offsets deteriorate the overall system performance. A compensation strategy to eliminate the effect of current measurement offsets in grid-connected inverters is proposed in this study. The validity of the proposed compensation strategy is verified through simulations and experiments. Results show that the proposed compensation strategy improves the performance of grid-connected inverters.