• Korean Journal of Cognitive Science
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• v.33 no.1
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• pp.51-75
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• 2022

Transcranial direct current stimulation (tDCS) is a non-invasive brain stimulation that is able to alter neuronal activity in particular brain regions. Many studies have researched how tDCS modulates neuronal activity and reorganizes neural networks. However it is difficult to conclude the effect of brain stimulation because the studies are heterogeneous with respect to the stimulation parameter as well as individual difference. It is not fully in agreement with the effects of brain stimulation. In particular few studies have researched the reason of variability of brain stimulation in response to time so far. The study investigated individual variability of brain stimulation based on circadian rhythm and chronotype. Participants were divided into two groups which are morning type and evening type. The experiment was conducted by Zoom meeting which is video meeting programs. Participants were sent experiment tool which are Muse(EEG device), tdcs device, cell phone and cell phone holder after manuals for experimental equipment were explained. Participants were required to make a phone in frount of a camera so that experimenter can monitor online EEG data. Two participants who was difficult to use experimental devices experimented in a laboratory setting where experimenter set up devices. For all participants the accuracy of 98% was achieved by SVM using leave one out cross validation in classification in the the effects of morning stimulation and the evening stimulation. For morning type, the accuracy of 92% and 96% was achieved in classification in the morning stimulation and the evening stimulation. For evening type, it was 94% accuracy in classification for the effect of brain stimulation in the morning and the evening. Feature importance was different both in classification in the morning stimulation and the evening stimulation for morning type and evening type. Results indicated that the effect of brain stimulation can be explained with brain state and trait. Our study results noted that the tDCS protocol for target state is manipulated by individual differences as well as target state.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• The Journal of Korean Academy of Prosthodontics
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• v.47 no.1
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• pp.39-45
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• 2009

Statement of problem: Recently precalcification treatment has been studied to shorten the period of the implant. Purpose: This study was performed to evaluate the effect of precalcification treatment of $TiO_2$ Nanotube formed on Ti-6Al-4V Alloy. Material and methods: Specimens of $20{\times}10{\times}2\;mm$ in dimensions were polished sequentially from #220 to #1000 SiC paper, ultrasonically washed with acetone and distilled water for 5 min, and dried in an oven at $50^{\circ}C$ for 24 hours. The nanotubular layer was processed by electrochemical anodic oxidation in electrolytes containing 0.5 M $Na_2SO_4$ and 1.0 wt% NaF. Anodization was carried out using a regulated DC power supply (Kwangduck FA, Korea) at a potential of 20 V and current density of $30\;㎃/cm_2$ for 2 hours. Specimens were heat-treated at $600^{\circ}C$ for 2 hours to crystallize the amorphous $TiO_2$ nanotubes, and precalcified by soaking in $Na_2HPO_4$ solution for 24 hours and then in saturated $Ca(OH)_2$ solution for 5 hours. To evaluate the bioactivity of the precalcified $TiO_2$ nanotube layer, hydroxyapatite formation was investigated in a Hanks' balanced salts solution with pH 7.4 at $36.5^{\circ}C$ for 2 weeks. Results: Vertically oriented amorphous $TiO_2$ nanotubes of diameters 48.0 - 65.0 ㎚ were fabricated by anodizing treatment at 20 V for 2 hours in an 0.5 M $Na_2SO_4$ and 1.0 NaF solution. $TiO_2$ nanotubes were composed with strong anatase peak with presence of rutile peak after heat treatment at $600^{\circ}C$. The surface reactivity of $TiO_2$ nanotubes in SBF solution was enhanced by precalcification treatment in 0.5 M $Na_2HPO_4$ solution for 24 hours and then in saturated $Ca(OH)_2$ solution for 5 hours. The immersion in Hank's solution for 2 weeks showed that the intensity of $TiO_2$ rutile peak increased but the surface reactivity decreased by heat treatment at $600^{\circ}C$. Conclusion: This study shows that the precalcified treatment of $TiO_2$ Nanotube formed on Ti-6Al-4V Alloy enhances the surface reactivity.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.100-101
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• 2012

The plasma damage free and room temperature processedthin film deposition technology is essential for realization of various next generation organic microelectronic devices such as flexible AMOLED display, flexible OLED lighting, and organic photovoltaic cells because characteristics of fragile organic materials in the plasma process and low glass transition temperatures (Tg) of polymer substrate. In case of directly deposition of metal oxide thin films (including transparent conductive oxide (TCO) and amorphous oxide semiconductor (AOS)) on the organic layers, plasma damages against to the organic materials is fatal. This damage is believed to be originated mainly from high energy energetic particles during the sputtering process such as negative oxygen ions, reflected neutrals by reflection of plasma background gas at the target surface, sputtered atoms, bulk plasma ions, and secondary electrons. To solve this problem, we developed the NBAS (Neutral Beam Assisted Sputtering) process as a plasma damage free and room temperature processed sputtering technology. As a result, electro-optical properties of NBAS processed ITO thin film showed resistivity of $4.0{\times}10^{-4}{\Omega}{\cdot}m$ and high transmittance (>90% at 550 nm) with nano- crystalline structure at room temperature process. Furthermore, in the experiment result of directly deposition of TCO top anode on the inverted structure OLED cell, it is verified that NBAS TCO deposition process does not damages to the underlying organic layers. In case of deposition of transparent conductive oxide (TCO) thin film on the plastic polymer substrate, the room temperature processed sputtering coating of high quality TCO thin film is required. During the sputtering process with higher density plasma, the energetic particles contribute self supplying of activation & crystallization energy without any additional heating and post-annealing and forminga high quality TCO thin film. However, negative oxygen ions which generated from sputteringtarget surface by electron attachment are accelerated to high energy by induced cathode self-bias. Thus the high energy negative oxygen ions can lead to critical physical bombardment damages to forming oxide thin film and this effect does not recover in room temperature process without post thermal annealing. To salve the inherent limitation of plasma sputtering, we have been developed the Magnetic Field Shielded Sputtering (MFSS) process as the high quality oxide thin film deposition process at room temperature. The MFSS process is effectively eliminate or suppress the negative oxygen ions bombardment damage by the plasma limiter which composed permanent magnet array. As a result, electro-optical properties of MFSS processed ITO thin film (resistivity $3.9{\times}10^{-4}{\Omega}{\cdot}cm$, transmittance 95% at 550 nm) have approachedthose of a high temperature DC magnetron sputtering (DMS) ITO thin film were. Also, AOS (a-IGZO) TFTs fabricated by MFSS process without higher temperature post annealing showed very comparable electrical performance with those by DMS process with $400^{\circ}C$ post annealing. They are important to note that the bombardment of a negative oxygen ion which is accelerated by dc self-bias during rf sputtering could degrade the electrical performance of ITO electrodes and a-IGZO TFTs. Finally, we found that reduction of damage from the high energy negative oxygen ions bombardment drives improvement of crystalline structure in the ITO thin film and suppression of the sub-gab states in a-IGZO semiconductor thin film. For realization of organic flexible electronic devices based on plastic substrates, gas barrier coatings are required to prevent the permeation of water and oxygen because organic materials are highly susceptible to water and oxygen. In particular, high efficiency flexible AMOLEDs needs an extremely low water vapor transition rate (WVTR) of $1{\times}10^{-6}gm^{-2}day^{-1}$. The key factor in high quality inorganic gas barrier formation for achieving the very low WVTR required (under ${\sim}10^{-6}gm^{-2}day^{-1}$) is the suppression of nano-sized defect sites and gas diffusion pathways among the grain boundaries. For formation of high quality single inorganic gas barrier layer, we developed high density nano-structured Al2O3 single gas barrier layer usinga NBAS process. The NBAS process can continuously change crystalline structures from an amorphous phase to a nano- crystalline phase with various grain sizes in a single inorganic thin film. As a result, the water vapor transmission rates (WVTR) of the NBAS processed $Al_2O_3$ gas barrier film have improved order of magnitude compared with that of conventional $Al_2O_3$ layers made by the RF magnetron sputteringprocess under the same sputtering conditions; the WVTR of the NBAS processed $Al_2O_3$ gas barrier film was about $5{\times}10^{-6}g/m^2/day$ by just single layer.

• Journal of the Korean Electrochemical Society
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• v.13 no.2
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• pp.116-122
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• 2010

A $Cu_3Si$ film electrode is obtained by Si deposition on a Cu foil using DC magnetron sputtering, which is followed by annealing at $800^{\circ}C$ for 10 h. The Si component in $Cu_3Si$ is inactive for lithiation at ambient temperature. The linear sweep thermammetry (LSTA) and galvano-static charge/discharge cycling, however, consistently illustrate that $Cu_3Si$ becomes active for the conversion-type lithiation reaction at elevated temperatures (> $85^{\circ}C$). The $Cu_3Si$ electrode that is short-circuited with Li metal for one week is converted to a mixture of $Li_{21}Si_5$ and metallic Cu, implying that the Li-Si alloy phase generated at 0.0 V (vs. Li/$Li^+$) at the quasi-equilibrium condition is the most Li-rich $Li_{21}Si_5$. However, the lithiation is not extended to this phase in the constant-current charging (transient or dynamic condition). Upon de-lithiation, the metallic Cu and Si react to be restored back to $Cu_3Si$. The $Cu_3Si$ electrode shows a better cycle performance than an amorphous Si electrode at $120^{\circ}C$, which can be ascribed to the favorable roles provided by the Cu component in $Cu_3Si$. The inactive element (Cu) plays as a buffer against the volume change of Si component, which can minimize the electrode failure by suppressing the detachment of Si from the Cu substrate.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.47-55
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• 2012

A discrete-time(DT) filter with high-order temporal moving average(TMA) using actively-weighted charge sampling is proposed in this paper. To obtain different weight of sampled charge, the variable transconductance OTA is used prior to charge sampler, and the ratio of charge can be effectively weighted by switching the control transistors in the OTA. As a result, high-order TMA operation can be possible by actively-weighted charge sampling. In addition, the transconductance generated by the OTA is relatively accurate and stable by using the size ratio of the control transistors. The high-order TMA filter has small size, increased voltage gain, and low parasitic effects due to the small amount of switches and sampling capacitors. It is implemented in the TSMC $0.18-{\mu}m$ CMOS process by TMA-$2^2$. The simulated voltage gain is about 16.7 dB, and P1dB and IIP3 are -32.5 dBm and -23.7 dBm, respectively. DC current consumption is about 9.7 mA.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.71-76
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• 2017

The electrical behavior and flexibility of the screen printed Ag circuits were investigated with infrared radiation sintering times and sintering temperatures. Electrical resistivity and radio frequency characteristics were evaluated by using the 4 point probe measurement and the network analyzer by using cascade's probe system, respectively. Electrical resistivity and radio frequency characteristics means that the direct current resistance and signal transmission properties of the printed Ag circuit. Flexibility of the screen printed Ag circuit was evaluated by measuring of electrical behavior during IPC sliding test. Failure mode of the Ag printed circuits was observed by using field emission scanning electron microscope and optical microscope. Electrical resistivity of the Ag circuits screen printed on Pl substrate was rapidly decreased with increasing sintering temperature and durations. The lowest electrical resistivity of Ag printed circuit was up to $3.8{\mu}{\Omega}{\cdot}cm$ at $250^{\circ}C$ for 45 min. The crack length arisen within the printed Ag circuit after $10{\times}10^4$ sliding numbers was 10 times longer than that of after $2.5{\times}10^4$ sliding numbers. Measured insertion loss and calculated insertion loss were in good agreements each other. Insertion loss of the printed Ag circuit was increased with increasing the number of sliding cycle.