• 전력전자학회논문지
• /
• 제25권4호
• /
• pp.261-268
• /
• 2020

Transformer saturation in full bridge (FB) isolated DC-DC converters is caused by uneven switching speeds and voltage drops in semiconductor devices and mismatched gate signals. In order to prevent transformer saturation, most popular and widely used approach is to insert a capacitor in series with the transformer windings. This study conducts extensive analyses on transformer saturation and the effect of DC blocking capacitors when they are placed in the primary or secondary windings of a transformer. The effect of the DC blocking capacitors is verified in voltage-fed and current-fed FB converters.

• Journal of Electrical Engineering and Technology
• /
• 제12권5호
• /
• pp.1902-1915
• /
• 2017

This paper presents the evaluation of a three-phase three-level DC-DC converter which achieves the soft switching condition for all switches in the circuit and uses the phase-shift PWM strategy to adjust electric power at the output side. According to the analysis, the operation modes can be categorized into two cases: in the first case, where the phase shift angle is less than 120 degrees and in the second case, where the phase shift angle is more than 120 degrees. The outer switches of the circuit operate under ZVS condition and the inner switches operate under ZVZCS condition. It has been discovered that under ZCS condition of the inner switches, when the blocking capacitors decrease, they make the voltage across the blocking capacitor higher so the current reduce rapidly. A three-phase three-level DC-DC converter has a maximum efficiency of 93.5% when its load is of 5.7 kW. The results from the experiment have been compared to the results obtained by the $MATLAB^{(R)}$ simulator in order to confirm the validity of the proposed converter.

• Journal of Power Electronics
• /
• 제19권6호
• /
• pp.1486-1495
• /
• 2019

Dealing with the DC link fault poses a technical problem for an HVDC based on a modular multilevel converter. The fault suppressing mechanisms of several sub-module topologies with DC fault current blocking capacity are examined in this paper. An improved half-bridge sub-module topology with double direction control switch is also designed to address the additional power consumption problem, and a sub-module topology called hybrid double direction blocking sub module (HDDBSM) is proposed. The DC fault suppression characteristics and sub-module capacitor voltage balance problem is also analyzed, and a self-startup method is designed according to the number of capacitors. The simulation model in PSCAD/EMTDC is built to verify the self-startup process and the DC link fault suppression features.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2002년도 춘계종합학술대회
• /
• pp.288-292
• /
• 2002

RF 회로에 적합한 새로운 형태의 on-chip ESD protection 방법을 제시하였다. RF 회로의 특성을 이용하여 DC blocking capacitor 앞에 short-circuited stub를 달아서 ESD 소자로 활용하였다. 특히 short-circuited stub를 매칭 회로의 일부로 사용하여 stub의 길이를 줄일 수 있다. 또한 short-circuited stub의 width와 metal의 성분으로 ESD threshold voltage를 쉽게 예측 가능하다. 기존의 ESD 방지 회로와 달리 RF 회로를 위한 ESD 방지 회로에서 문제시되던 기생 capacitance 성분에 대한 문제점을 해결 할 수 있었다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2011년도 제42회 하계학술대회
• /
• pp.1608-1609
• /
• 2011

In this study, in order to develop the evaluation method for XLPE materials for HVDC cables, DC/Impulse superposition testing system was builded up. Throughout the P-spice simulation, optimal values of the protection resistor for the DC generation system and the blocking capacitor for the Impulse generator were calculated. DC/Impulse superposition system showed good result maintaining their proper wave shapes and amplitudes. This system would be planned to apply to the evaluation of XLPE materials for HVDC cables.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2019년도 추계학술대회
• /
• pp.40-42
• /
• 2019

절연형 전력변환기에서 사용되는 고주파 변압기는 반도체 소자의 스위칭 시간, 전압 강하, 게이트 신호의 불균형 등으로 인해 변압기의 양과 음의 전압-시간(volt-second)에 차이가 발생할 수 있다. 본 논문은 절연형 풀브리지 타입 전력변환기에서 DC 성분에 의한 변압기 코어의 포화문제를 방지하기 위해 사용되는 DC 블로킹 캐패시터(DC blocking capacitor)의 설계 방법에 대해 분석하고 실험을 통해 증명한다.

• 한국전자파학회논문지
• /
• 제12권3호
• /
• pp.432-438
• /
• 2001

본 논문은 Defected Ground Structure(DGS)를 DC block에 적용한 후 DC block의 부분인 λ/4-결합 선로의 간격과 길이의 변화를 EM 시뮬레이션과 실제 제작을 통하여 알라보았다. 그 결과 일반적인 DC block을 사용할때와 동일 출력 조건하에서 DGS 구조의 DC block의 λ/4-결합선로사이의 간격이 0.1 mm에서 0.46 mm로 0.36 mm만큼 늘어나고λ/4-결합 선로의 길이는 71.7 mm에서 13.32 mm로 4.5 mm만큼 줄어드는 것을 알 수 있었다. 또한 Blocking 캐패시터, 일반적인 DC block, DGS 구조의 DC block을 사용하는 세 종류의 전력증폭기를 제작한 후 특성을 확인해 보았다. 먼저 각 증폭기의 산란 파라미커 특성을 살펴본 결과 3.2$\pm$0.05 GHz의 주파수 대역에서 세 증폭기 모두 유사한 이득 특성과 산란 파라미터 특성을 갖음을 알수 있었다. 그리고 3.2 GHz의 CW 신호를 인가하여 주신호의 출력 전력이 25dBm 일 때 하모닉 특성을 스펙트럼 분석기로 분석한 결과 캐패시티를 사용시에는 주신호와 2차 하모닉 성분과의 차이가 -44.83dBc 일반적인 DC block과 DGS DC block 사용시에는 -66.84와 -64.33 dBc로서 일반적인 DC block 사용시와 DGS block 사용시에 하모닉 특성이 거의 일치함을 확인하였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
• /
• pp.125-128
• /
• 2006

This paper presents a novel type soft switching PWM power frequency AC-AC converter using bidirectional active switches or single phase utility frequency AC-high frequency AC matrix converter. This converter can directly convert utility frequency AC (UFAC, 50Hz/60Hz) power to high frequency AC (HFAC) power ranging more than 20kHz up to 100kHz. A novel soft switching PWM prototype of high frequency multi-resonant PWM controlled UFAC-HFAC matrix converter using antiparallel one-chip reverse blocking IGBTs manufactured by IXYS corp. is based on the soft switching resonance with asymmetrical duty cycle PWM strategy. This single phase UFAC-HFAC matrix converter has some remarkable features as electrolytic capacitor DC busline linkless topology, unity power factor correction and sine-wave line current shaping, simple configuration with minimum circuit components, high efficiency and downsizing. This series load resonant UFAC-HFAC matrix converter, incorporating bidirectional active power switches is developed and implemented for high efficiency consumer induction heated food cooking appliances in home uses and business-uses. Its operating performances as soft switching operating ranges and high frequency effective power regulation characteristics are illustrated and discussed on the basis of simulation and experimental results.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2001년도 전력전자학술대회 논문집
• /
• pp.364-367
• /
• 2001

ZVS Full-bridge converter is widely used in medium power level(1-3kW). ZVS can be designed within a limited load range and ZVS failure at light load condition is assumed to be acceptable within the given efficiency and thermal constraints. However, unbalanced ZVS resonant energy caused by dc blocking capacitor may alleviate the switching loss problem at light load condition. ZVS resonant energy is unbalanced by do blocking capacitor. This problem causes loss and heat concentration of a switch leg, In this paper, this problem is analyzed, and a novel control method is proposed to solve the problem.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
• /
• pp.301-303
• /
• 2001

In this paper we present a Capacitor Charging Power Supply (CCPS) using a series-resonant three-level inverter topology to improve voltage regulation and use semiconductor switches having low blocking voltage capability such as MOSFETs. This inverter can be operated with two modes, Full Power Mode (FPM) and Half Power Mode (HPM). In FPM inverter supplies the high frequency step up transformer with full DC-link voltage and in HPM with half DC-link voltage. HPM switching method will be adopted when CCPS output voltage reaches the preset target value and operates in refresh mode-charge is maintained on the capacitor. In this topology each semiconductor devices blocks a half of the DC-link voltage[2]. A 15kW, 30kV CCPS has been built and will be tested for an electric precipitator application. The CCPS operates from an input voltage of 500VDC and has a variable output voltage between 10 to 30kV and 1kHz repetition rate at 44nF capacitive load [3]. A resonant frequency of 67.9kHz was selected and a voltage regulation of $0.83\%$ has been achieved through the use of half power mode without using the forced cut off the switch current [1]. The theory of operation, circuit topology and test results are given.