• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.4
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• pp.291-296
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• 2015

Transmission line is exposed to a large area, and then faults are likely to occur than the other component of power system. When a fault occurs on a transmission line, fault locator helps fast recovery of power supply on power system. This paper deals with the design of a digital fault locator for improvement accuracy of the fault distance estimation and a fault occurrence position for transmission line. The algorithm of a fault locator uses a DC offset removal filter and DFT filter. The algorithm utilizes a fault data of GPS time synchronized. The computed fault information is transmitted to the other side substation through communication. The digital fault locator includes MPU module, ADPU module, SIU module, and a power module. The MMI firmware and software of the fault locator was implemented.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.38-41
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• 2001

This paper presents a digital current differential protection algorithm for a transformer in power system. This algorithm uses an FIR filter to improve the performance of the relay. This paper presents a practical method setting the operating slope of the relay and reduce ct mismatch. A series of EMTP simulation results have shown effectiveness of the algorithm under various type of transformers and conditions.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.57-63
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• 2015

Fault currents characteristics contain decaying DC offset. First cycle peak value of fault currents is higher than steady-state fault current value. These characteristics can affect the operation of protective device. To reduce the asymmetric fault current, the method using a series connection of two hybrid-type Superconducting Fault Current Limiter(SFCL) components, an auxiliary SFCL and a main SFCL, has been proposed. The auxiliary SFCL limits the first half cycle fault current, while main SFCL limits the steady state fault currents. This paper proposed a decision method of the optimal insertion resistance of auxiliary and main SFCL components. To verify the effectiveness of proposed scheme, the various simulations are performed by using Electromagnetic Transient Program(EMTP).

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.1
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• pp.27-32
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• 2017

This paper presents a Daubechies wavelet-based fault detection method for fault identification in transmission lines. After the Daubechies wavelet coefficients are calculated, the proposed algorithm has been implemented difference equation using C language. We have modeled a 154kV transmission line using the ATPDraw software and have acquired test data. In order to evaluate effects of DC offset, simulations carried out while varying an inception angle of the voltage $0^{\circ}$, $45^{\circ}$, $90^{\circ}$. For performance evaluation, fault distance was varied. As we can see from the off-line simulation, the proposed algorithm shows rapid and accurate fault detection. Also we can see the proposed algorithm is not affected by the fault inception angle change.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.435-436
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• 2013

본 논문에서는 효율 개선을 위하여 변압기를 구비하지 않은 계통 연계형 전력변환장치에서의 직류분(DC offset) 검출에 대하여 알아본다. 변압기를 사용하지 않음으로써, 교류 출력에 직류 성분이 혼입하여 계통에 유입되는 경우 직류 성분이 주상변압기 등에 편자 현상 등으로 계통이나 다른 수용가 설비에 고장을 일으킨다. 스위칭 등의 이상에 따른 직류가 계통에 유출되는 것을 시뮬레이션을 통하여 확인해 보고 직류 검출하는 방법을 확인하도록 한다.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.5
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• pp.711-720
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• 1994

A distance relaying algorithm for detecting faults at power transmission line is presented in this paper. The algorithm is based on differential equation from relaton between voltage and current, which is composed of lumped resistance and inductance. During the fault transient state,the voltage and current signals are severely distorted due to the exponentially decaying DC offset and high frequency components, In spite of using small data, the presented integral method to evaluate R and L from voltage and current has high performance against these harmonics including DC offset. Therefore, the presented algorithm can be implemented with only a low order anti-aliasing analog filter and dosen't need any digital filter to remove specific components.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.1
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• pp.68-71
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• 2020

As a T-type three-level PWM converter has several intrinsic advantages, it has been widely studied for many applications. However, it requires an additional voltage control loop for balancing each DC link voltage. Generally, satisfying this requirement involves the use of an offset voltage to provide a neutral point current without affecting other variables, such as the total DC link voltage and three-phase input current. In this study, the theoretical relationship between the offset voltage and the neutral point current is analyzed. The results can be beneficial for effective voltage balancing controller design. The effectiveness of the analytical modeling is verified by simulation and experimental results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.299-301
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• 2014

본 논문에서는 직류 오프셋 (DC-offset) 제거 기능을 가진 저 전력 자동 이득 조절 증폭기 (PGA, Programmable Gain Amplifier)를 제안한다. 이러한 회로는 직류 오프셋 문제점을 해결하기 위해 기존의 gm-boosting 증폭기를 변형한 디지털 이득 제어 방식으로 설계되어 있기 때문에 우수한 선형성을 가진다. 또한 특수 목적에 맞도록 그 이득을 6dB에서 60dB까지 7단계로 조절 가능하며, 밀러효과를 이용한 AC-coupling 방식으로 큰 값의 유동적인 커패시터와 저항을 구현하여 직류 오프셋을 제거한다. 제안한 PGA는 기존 회로에 비해 0.2dB 보다 작은 이득오차와 0.47mW의 낮은 소비전력 특성을 보였다.

• ETRI Journal
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• v.29 no.3
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• pp.408-410
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• 2007

A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc-decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ${\pm}0.6$ LSB and ${\pm}1.6$ LSB, respectively.