• 한국정보통신학회논문지
• /
• 제18권8호
• /
• pp.1827-1832
• /
• 2014

4세대 이동통신시스템 '롱텀에볼루션(LTE)'의 핵심기술인 다중 송수신 (MIMO) 안테나 시스템은 추가적인 주파수나 송신전력의 할당 없이도 채널 용량을 안테나 수에 비례하여 증가시킬 수 있는 장점으로 인해 데이터 전송 속도를 획기적으로 늘리는 기술로 4세대 이동통신기술 진화의 핵심기술로 꼽히고 있다. 본 논문은 다중 송수신 안테나 시스템에서 사용되는 2개 이상의 DAC 대신에 고속 DAC와 아날로그 스위치를 각각 한 개씩 사용하여 기존 방식의 장점을 유지하며 설계비용 감소, 물리적 크기 축소화 등 경제적 효율을 증가시킬 수 있는 MIMO 시스템에서 데이터 컨버터를 줄일 수 있는 방안을 제안한다.

• Progress in Superconductivity
• /
• 제3권2호
• /
• pp.172-177
• /
• 2002

Superconductive digital to analog converters (DAC) based on Josephson effect produce the voltage steps with high precision and good stability Therefore, they can be applied to obtain a very accurate ac voltage standard. In this paper, we made a simulation study of Rapid Single Flux Quantum (RSFQ) DAC. RSFQ DAC was composed of Non-destructive Head Out (NDRO) cells, T flip-flops, D flip-flops, Splitters, and Confluence Buffers. Confluence Buffer was used in resetting the DACs. We also obtained operating margins of the important circuit parameters in simulations.

• Journal of Information Display
• /
• 제2권2호
• /
• pp.1-6
• /
• 2001

A $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with a new integrated 8-bit parallel-serial digital data driver was proposed and designed. For high resolution, the proposed parallel-serial digital driver used serial video data rather than parallel ones. Thus, digital circuits for driving one column line could be integrated within very small width. The parallel-serial digital data driver comprised of shift registers, latches, and serial digital-to-analog converters (DAC's). We designed a $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with integrated 8-bit parallel-serial digital data drivers by a circuit simulator which has physical-based analytical model of poly-Si TFT's. The fabricated shift register well operated at 2 MHz and $V_{DD}$=10V and the fabricated poly-Si TFT serial DAC's, which converts serial digital data to an analog signal, could convert one bit within $2.8{\mu}s$. The driver circuits for one data line occupied $8100{\times}50{\mu}m^2$ with $4{\mu}m$ design rule.

• Journal of electromagnetic engineering and science
• /
• 제17권1호
• /
• pp.39-43
• /
• 2017

In this paper, a systematic and statistical calibration technique was implemented to calibrate a high-speed signal converting system containing multiple digital-to-analog converters (DACs). The systematic error (especially the imbalance between DACs) in the current combining network of the multi-DAC system was modeled and corrected by calculating the path coefficients for individual DACs with wideband reference signals. Furthermore, by applying a Kalman filter to suppress noise from quantization and clock jitter, accurate coefficients with minimum noise were identified. For correcting an arbitrary waveform generator with two DACs, a co-simulation platform was implemented to estimate the system degradation and its corrected performance. Simulation results showed that after correction with 4.8 Gbps QAM signal, the signal-to-noise-ratio improved by approximately 4.5 dB and the error-vector-magnitude improved from 4.1% to 1.12% over 0.96 GHz bandwidth.

• 한국초전도학회:학술대회논문집
• /
• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
• /
• pp.160-164
• /
• 2000

Digital to analog converters based on the Josephson effect are promising for voltage standard, because they produce voltage steps with high precision and good stability. In this paper, we made a simulation study on RSFQ D/A converter. RSFQ D/A converter was composed of NDRO cells, T(toggle) flip-flops, D flip-flops, Splitters and Confluence Buffers. Confluence Buffer was used to reset the D/A converter. We also obtained operating margins of the important circuit values by simulational experiments.

• 대한기계학회논문집A
• /
• 제28권12호
• /
• pp.1923-1930
• /
• 2004

This paper presents digital microflow controllers(DMFC), where a fluidic digital-to-analog converter(DAC) is used to achieve high-linearity, fine-level flow control for applications to precision biomedical dosing systems. The fluidic DAC, composed of binary-weighted flow resistance, controls the flow-rate based on the ratio of the flow resistance to achieve high-precision flow-rate control. The binary-weighted flow resistance has been specified by a serial or a parallel connection of an identical flow resistor to improve the linearity of the flow-rate control, thereby making the flow-resistance ratio insensitive to the size uncertainty in flow resistors due to micromachining errors. We have designed and fabricated three different types of 4-digit DMFC: Prototype S and P are composed of the serial and the parallel combinations of an identical flow resistor, while Prototype V is based on the width-varied flow resistors. In the experimental study, we perform a static test for DMFC at the forward and backward flow conditions as well as a dynamic tests at pulsating flow conditions. The fabricated DMFC shows the nonlinearity of 5.0% and the flow-rate levels of 16(2$^{N}$) for the digital control of 4(N) valves. Among the 4-digit DMFC fabricated with micromachining errors, Prototypes S and P show 27.2% and 27.6% of the flow-rate deviation measured from Prototype V, respectively; thus verifying that Prototypes S and P are less sensitive to the micromachining error than Prototype V.V.

• 한국음향학회지
• /
• 제24권1호
• /
• pp.11-20
• /
• 2005

본 논문에서는 PLL (Phase Locked Loop)없이 동작할 수 있는 S/PDIF (Sony Philips Digital Interface) 수신기의 연구에 관하여 다룬다. 현재 대부분의 오디오 장치와 오디오 프로세서에서 S/PDIF 수신기가 사용되고 있음에도 불구하고, 국내에서는 이에 관한 연구가 많지 않은 실정이다. 현재 사용되고 있는 S/PDIF 수신용 상용 DAC(Digital-to-Analog Converters) 칩들은 모두 내부에 PLL 회로를 포함하고 있다. PLL 회로는 S/PDIF 디지틸 신호로부터 클럭 정보를 뽑아내고 클럭과 입력 신호간의 동기화를 맞추는 역할을 한다. 그러나, PLL 회로는 "아날로그 회로"라는 특성 때문에 VLSI (Very Large Scale Integrated Ciruits)회로의 SOCs (System On Chips)설계에 있어 많은 어려움을 야기한다. 본 논문에서는 PLL 회로 없이 순수 디지털 회로로만 구현된 S/PDIF 수신기를 제안하였다. 제안된 수신기의 핵심 아이디어는 16 MHz의 기본 클럭과 S/PDIF 신호의 속도비를 이용한다는 것이다. 본 논문에서는 수십만개의 S/PDIF 입력 신호에 대한 디코딩 확인 후, PLL같은 아날로그 회로 없이 순수 디지틸 회로만으로 S/PDIF 수신기를 설계할 수 있음을 확인하였다. 제안된 S/PDIF 수신기는 SOC 설계용 If로서 활용될 수 있을 것으로 본다.

• 센서학회지
• /
• 제25권5호
• /
• pp.349-353
• /
• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

• 대한전자공학회논문지SD
• /
• 제48권10호
• /
• pp.39-45
• /
• 2011

본 논문에서는 선택적으로 클럭 신호를 입력하는 저 전력 전류구동 10비트 D/A 변환기 회로를 제안하였다. 제안된 DAC에서는 데이터가 변하지 않는 전류원 셀에 클럭 신호를 제한하여 클럭 전력 소모를 줄였다. 제안된 DAC는 1.2V 0.13${\mu}m$ CMOS 공정을 사용하여 제작되었으며, DAC 칩 면적은 0.21$mm^2$였다. 200MHz 샘플링 주파수와 1MHz 입력 신호 주파수에서, 제안된 DAC의 전력 소모량은 4.46mW였다. 클럭 신호에서 소모되는 전력은 입력 주파수가 1.25MHz와 10MHz일 때 각각 30.9%와 36.2%로 감소되었다. 측정된 SFDR은 입력주파수가 1MHz와 50MHz일 때 각각 72.8dB와 56.1dB였다.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2003년도 ICCAS
• /
• pp.1066-1070
• /
• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.