• Journal of Korean Society for Geospatial Information Science
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• v.25 no.2
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• pp.67-74
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• 2017

The D-InSAR is a technique for precisely measuring the subsidence of subsidence using difference of two SAR images. In order to calculate the subsidence using D-InSAR, a high coherence between master image and the slave image is essential. Since the existing D-InSAR method calculates the displacement based on the total coherence, the accuracy of the subsidence is lowered when the coherence map contains mountains or bare-land. In order to solve this problem, in this study, a point having a temporal coherence and spatial coherence of 0.7 or more was extracted to form TIN, and the subsidence was calculated based on this TIN. In addition, we compared the existing D-InSAR technique with the new D-InSAR technique considering spatial and temporal coherence. As a result, the new D-InSAR technique showed smaller standard deviation, relative variance, variation coefficient and quadrature deviation than the existing D-InSAR technique. It is also easy to grasp the trend of the subsidence.

• Journal of the Korean Geotechnical Society
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• v.38 no.11
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• pp.43-54
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• 2022

The settlement at the railroad foundation is often the leading cause of track irregularity and potential derailment. The control of such deformation is considered necessary in track maintenance practice. Nevertheless, the monitoring process performed by in situ surveying requires an excessive amount of manpower and cost. The InSAR, a remote sensing technique by RADAR satellite, is used to overcome such a burden. The PS-InSAR technique is preferred for a long-term precise monitoring method. However, this study aims to obtain relatively brief analysis results from only two satellite images using the D-InSAR technique, while a minimum of 25 images are required for PS-InSAR. This study verifies the precision of D-InSAR within a few millimeters by inspecting railroad facilities and land settlements in Korea Railroad Research Institute's test track with images from TerraSAR-X Satellite. Multiple corner reflectors were adopted and installed on an embankment and the building roof to raise the surface reflectivity. Those reflectors were slightly adjusted periodically to verify the detecting performance. The results revealed the optimum distance between corner reflectors. Further, the deformation of railway tracks, slopes, and concrete structures was analyzed successively. In conclusion, this study indicates that the D-InSAR technique effectively monitors the short-term deformation of a broad area such as railway structures.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.2
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• pp.118-127
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• 2018

In this work, we have designed and manufactured radar target simulation equipment for the performance analysis of synthetic aperture radar(SAR) systems. First, we have explained the function and performance specification of the target simulation equipment and point target scenario generation for validation of the SAR system. In addition, we have developed a simple and accurate calibration method for the time delay of the SAR system using the manufactured target simulation equipment. We have analyzed the point target impulse response function of the SAR image acquired using the SAR system and the target simulation equipment. It was observed that the measured peak to side lobe ratio(=-13.25 dB) and resolution(=0.49 m) are in good agreement with the corresponding theoretical values.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.7
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• pp.1858-1872
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• 2023

With the advance of radar technologies, the availability of synthetic aperture radar (SAR) images increases. To improve application of SAR images, a management system for SAR images is proposed in this paper. The system provides trainable land cover classification module and display of SAR images on the map. Users of the system can create their own classifier with their data, and obtain the classified results of newly captured SAR images by applying the classifier to the images. The classifier is based on convolutional neural network structure. Since there are differences among SAR images depending on capturing method and devices, a fixed classifier cannot cover all types of SAR land cover classification problems. Thus, it is adopted to create each user's classifier. In our experiments, it is shown that the module works well with two different SAR datasets. With this system, SAR data and land cover classification results are managed and easily displayed.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.149-157
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• 2008

If we use the microwave of SAR, we can observe ocean in spite of severe weather or night time. The sea surface image of SAR has numerous information about atmospheric phenomena related to surface wind field. The extracted wind information from SAR can be used diversely. In order to extract sea wind speed from SAR image, a generated wind direction from SAR and sigma nought should be input into wind model. Therefore, wind speed can be obtained by input wind direction into CMOD5 Model. Azimuth angle using CMOD5 Model is generated by added $90^{\circ}$ to Look angle which is extracted from SAR data file. A gained wind direction spectrum from SAR image has $180^{\circ}$ ambiguity because of 2D-FFT. This ambiguity should decide to use the location of land, wind direction in field or the result of numerical model. Consequently, wind direction using 2D-FFT is $3^{\circ}{\sim}7^{\circ}$ differences with actual surveying data. Wind speed by CMOD5 model is similar to actual surveying data as below 2m/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).