• Journal of the Korea Society for Simulation
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• v.19 no.3
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• pp.81-89
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• 2010

Recent modeling and simulation technology is being used in various fields. Especially in the field of military, Simulation-Based Acquisition (SBA) is recognized as a essential policy. To effectively carry out SBA, modeling and simulation techniques should be applied in the whole life-cycle for the weapon system development, and simulation architecture framework which provides easily reusable and interoperability is needed. Through reusability and interoperability, the costs of constructing the integrated collaborate environment for simulation based acquisition can be minimized. In this study, we define requirements, issues for enhancing reusability and interoperability, and propose simulation framework as a solution of the problem including structural design. Proposing simulation framework provides common functions for producing simulator as reusable units and easily changeable structure on user's purpose. In addition, we provide the result for applying simulation framework to our project.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.17 no.2
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• pp.183-202
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• 2019

For design and performance assessment of a high-level radioactive waste (HLW) disposal system, it is necessary to understand the characteristics of coupled thermo-hydro-mechanical (THM) behavior. However, in previous studies for the Korean Reference HLW Disposal System (KRS), thermal analysis was performed to determine the spacing of disposal tunnels and interval of disposition holes without consideration of the coupled THM behavior. Therefore, in this study, TOUGH2-MP/FLAC3D is used to conduct THM modeling for performance assessment of the Korean Reference HLW Disposal System (KRS). The peak temperature remains below the temperature limit of $100^{\circ}C$ for the whole period. A rapid rise of temperature caused by decay heat occurs in the early years, and then temperature begins to decrease as decay heat from the waste decreases. The peak temperature at the bentonite buffer is around $96.2^{\circ}C$ after about 3 years, and peak temperature at the rockmass is $68.2^{\circ}C$ after about 17 years. Saturation of the bentonite block near the canister decreases in the early stage, because water evaporation occurs owing to temperature increase. Then, saturation of the bentonite buffer and backfill increases because of water intake from the rockmass, and bentonite buffer and backfill are fully saturated after about 266 years. The stress is calculated to investigate the effect of thermal stress and swelling pressure on the mechanical behavior of the rockmass. The calculated stress is compared to a spalling criterion and the Mohr-Coulumb criterion for investigation of potential failure. The stress at the rockmass remains below the spalling strength and Mohr-Coulumb criterion for the whole period. The methodology of using the TOUGH2-MP/FLAC3D simulator can be applied to predict the long-term behavior of the KRS under various conditions; these methods will be useful for the design and performance assessment of alternative concepts such as multi-layer and multi-canister concepts for geological spent fuel repositories.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.1
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• pp.9-26
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• 2005

In the pursuit of ever higher levels of performance, recent computer systems have made use of deep pipeline, dynamic scheduling and multi-issue superscalar processor technologies. In this situations, branch prediction schemes are an essential part of modem microarchitectures because the penalty for a branch misprediction increases as pipelines deepen and the number of instructions issued per cycle increases. In this paper, we propose a novel branch prediction scheme, direction-gshare(d-gshare), to improve the prediction accuracy. At first, we model a neural network with the components that possibly affect the branch prediction accuracy, and analyze the variation of their weights based on the neural network information. Then, we newly add the component that has a high weight value to an original gshare scheme. We simulate our branch prediction scheme using Simple Scalar, a powerful event-driven simulator, and analyze the simulation results. Our results show that, compared to bimodal, two-level adaptive and gshare predictor, direction-gshare predictor(d-gshare. 3) outperforms, without additional hardware costs, by up to 4.1% and 1.5% in average for the default mont of embedded direction, and 11.8% in maximum and 3.7% in average for the optimal one.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.17 no.4
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• pp.54-62
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• 2018

As a part of realization of artificial intelligence signal(AI Signal), this study proposed an actuated signal algorithm based on vehicle queue length that estimates in real time by deep learning. In order to implement the algorithm, we built an API(COM Interface) to control the micro traffic simulator Vissim in the tensorflow that implements the deep learning model. In Vissim, when the link travel time and the traffic volume collected by signal cycle are transferred to the tensorflow, the vehicle queue length is estimated by the deep learning model. The signal time is calculated based on the vehicle queue length, and the simulation is performed by adjusting the signaling inside Vissim. The algorithm developed in this study is analyzed that the vehicle delay is reduced by about 5% compared to the current TOD mode. It is applied to only one intersection in the network and its effect is limited. Future study is proposed to expand the space such as corridor control or network control using this algorithm.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.14 no.4
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• pp.40-51
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• 2015

This study analysis traffic phase order alternatives to maximize throughput. According to theoretical analysis alternative2(EW: left turn after through, NS: through after left turn) and alternative5(EW: through after left turn, NS: left turn after through) can minimize the maximum delay. Both alternatives split the phase that have the same destination link under the whole cycle length. This shows that phase order alternative can effect to the fully saturated intersection. In side of simulation analysis by microscopic traffic simulator PTV VISSIM F 7.0, each phase order alternatives can't effect throughput under the non saturated condition. However under the saturated condition, the average controlled delay of the intersection has been changed by phase order alternatives. The simulation analysis shows that alternative2 and alternative5 increase throughput 3.8% to 5.1% under the saturated condition.

• Journal of Korean Society of Transportation
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• v.33 no.5
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• pp.478-487
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• 2015

This study proposed a Variable Speed Limits(VSL) algorithm to use traffic information based on Cumulative Demand-Capacity Analysis and evaluated its performance. According to the analysis result, the total of delay consisted of 3 separate parts. There was no change in total travel time although the total of delay decreased. These effects was analysed theoretically and then, evaluated through VISSIM, a microscopic simulator. VISSIM simulation results show almost same as those of theoretical analysis. Furthermore in SSAM analysis with VISSIM simulation log, the number of high risk collisions decreased 36.0 %. However, the total delay decrease effect is not real meaning of decrease effect because the drivers' desired speed is same whether the VSL model is operated or not. Nevertheless this VSL model maintains free flow speed for longer and increases the cycle of traffic speed fluctuation. In other words, this is decrease of delay occurrence and scale. The decrease of speed gap between upstream and downstream stabilizes the traffic flow and leads decrease number of high risk collision. In conclusion, we can expect increase of safety through total delay minimization according to this VSL model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Clean Technology
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• v.26 no.2
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• pp.96-101
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• 2020

In this paper, the commercial feasibility of trigeneration, producing heat, power, and hydrogen (CHHP) and using biogas derived from macroalgae (i.e., seaweed biomass feedstock), are investigated. For this purpose, a commercial scale trigeneration process, consisting of three MW solid oxide fuel cells (SOFCs), gas turbine, and organic Rankine cycle, is designed conceptually and simulated using Aspen plus, a commercial process simulator. To produce hydrogen, a solid oxide fuel cell system is re-designed by the removal of after-burner and the addition of a water-gas shift reactor. The cost of each unit operation equipment in the process is estimated through the calculated heat and mass balances from simulation, with the techno-economic analysis following through. The designed CHHP process produces 2.3 MW of net power and 50 kg hr^-1 of hydrogen with an efficiency of 37% using 2 ton hr^-1 of biogas from 3.47 ton hr^-1 (dry basis) of brown algae as feedstock. Based on these results, a realistic scenario is evaluated economically and the breakeven electricity selling price (BESP) is calculated. The calculated BESP is ¢10.45 kWh^-1, which is comparable to or better than the conventional power generation. This means that the CHHP process based on SOFC can be a viable alternative when the technical targets on SOFC are reached.

• Journal of Energy Engineering
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• v.23 no.2
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• pp.28-34
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• 2014

Automatic transmission fluid (ATF) is used for automatic transmissions in the vehicle as the characterized fluid. Recently, the vehicle manufacture usually guarantee for fluid change over 80000~100000 km mileage or no exchange, but most drivers usually change ATF below every 50000 km driving in Republic of Korea. It can cause to raise environmental contamination by used ATF and increase the cost of driving by frequently ATF change. In this study, we investigate the various physical properties such as flash point, fire point, pour point, kinematic viscosity, cold cranking simulator, total acid number, and metal component concentration for fresh and used ATF after driving (50000 km, 100000 km). The result showed that the total acid number, pour point, Fe, Al and Cu component had increased than fresh ATF, but 2 kind of used oil (50000 km and 100000km) had similar physical values and metal component concentration.