• 전기전자학회논문지
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• 제12권4호
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• pp.211-216
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• 2008

이 논문은 MOS 전류모드 논리 (MOS current-mode logic circuit, MCML) 회로를 이용하여 저 전력 특성을 갖는 8${\times}$8 비트 병렬 곱셈기를 설계하였다. 설계한 곱셈기는 회로가 동작 하지 않을 때의 정적 전류의 소모를 최소화하기 위하여 슬립 트랜지스터 (sleep-transistor)를 이용하여 저 전력 MOS 전류모드 논리회로를 구현하였다. 설계한 곱셈기는 기존 MOS 전류모드 논리회로에 비해 대기전력소모가 1/50으로 감소하였다. 또한, 이 회로는 기존 MOS 전류모드 논리회로에 비해 전력소모에서 10.5% 감소하였으며, 전력소모와 지연시간의 곱에서 11.6%의 성능 향상이 있었다. 이 회로는 삼성 0.35${\mu}m$ 표준 CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

• 한국산학기술학회논문지
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• 제11권10호
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• pp.3905-3910
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• 2010

본 논문에서는 3차 체비세프 전류모드 필터가 1.8V-$0.18{\mu}m$ CMOS 파라메터로써 설계되었다. 전류모드 필터의 기본 회로는 제안된 전압제어 주파수 가변 전류모드 적분기로 구성되었다. 제안된 전류모드 적분기를 사용함으로써 필터의 차단주파수가 가변될 수 있으며 또한 전체 소비전력을 줄 일 수 있다. HSPICE 시뮬레이션 결과, 필터의 차단주파수는 1.2MHz에서 10.1MHz로 조절되었고 전체 소비전력은 1.8V 공급전압에서 2.85mW으로 확인되었다.

• 전기학회논문지P
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• 제58권1호
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• pp.20-26
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• 2009

In this paper, the switching mode conversion type pulse charger by fly-back converter method for lead battery of the solar cell generator equipment is proposed. And we propose the control circuit and design method of insulated switching mode convert type pulse charger by fly-back convert method in the lead battery. The proposed system can minimize the current consumption by digital pulse. Also the proposed system can generate the constant 10[KHz] frequency, transmit the signal with main control system in the power control system. And it supervises the state of lead battery using one chip micro processor. The proposed the switching mode conversion type pulse charger by the fly-back converter method can charge fast and stabilize lead battery with nominal value 12[V], 20[AH]. Also we propose the design procedure of the power control circuit for turn ratio of fly-back inductor and determining method of values such as the charging current, bulk current, partial current, over current value and fixed charging voltage. The experiment results for the voltage and current wave for partial, bulk, over and fixed charging period show the good charging effect and performance. And the PCB and internal coupling diagram of the switching mode conversion type pulse charger by fly-back converter method is presented.

• 한국진공학회지
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• 제5권1호
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• pp.85-92
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• 1996

The external electricla characteristics of helicon wave plasmas were measured over a wide range of RF power and magnetic filed. External parameters. such as antenna voltage , current, phase shift, and interanl parameter, electron density were measured at 7MHz, 1mTorr Ar discharge . The equivalent discharge resistance and reactance, and the power transfer efficiency were calculated through these measurements. There are a helicon mode which produces high density plasma by helicon wave and a lowmode which produces low density plasma by capaictive electric field. In case of the helicon mode, the anternna voltage and current were lower than those of the low-mode. The phase difference between voltage and current decreased suddenly at the transition point from the low-mode to the helicon mode. Equivalent resistance and power efficiency increased and reactance decreased suddenly at the transition point. These results mean that the power transperred to plasma and the nutual coupling between the antenna and plasma increase as the mode changes from the low-mode to the helicon mode.

• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1593-1599
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• 2017

This paper presents a multi-channel light-emitting diode (LED) driver IC with a current-mode current regulator. The proposed current regulator replaces resistors for current sensing with a sequentially controlled single current sensor and a single regulation loop for sensing and regulating all LED channel currents. This minimizes the current mismatch among the LED channels and increases voltage headroom or, equivalently, power efficiency. The proposed LED driver IC was fabricated in a $0.35-{\mu}m$ BCD 60-V high voltage process, and the chip area is $1.06mm^2$. The measured maximum power efficiency is 93.4 % from a 12-V input, and the inter-channel current error is smaller than as low as ${\pm}1.3%$ in overall operating region.

• 센서학회지
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• 제21권1호
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• pp.1-6
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• 2012

Using a current-mode multiple reset, a current-to-voltage(I-V) converter with a wide dynamic range was produced. The converter consists of a trans-impedance amplifier(TIA), an analog-to-digital converter(ADC), and an N-bit counter. The digital output of the I-V converter is composed of higher N bits and lower bits, obtained from the N-bit counter and the ADC, respectively. For an input current that has departed from the linear region of the TIA, the counter increases its digital output, this determines a reset current which is subtracted from the input current of the I-V converter. This current-mode reset is repeated until the input current of the TIA lies in the linear region. This I-V converter is realized using 0.35 ${\mu}m$ LSI technology. It is shown that the proposed I-V converter can increase the maximum input current by a factor of $2^N$ and widen the dynamic range by $6^N$. Additionally, the I-V converter is successfully applied to a photometric sensor.

• 한국전자통신학회논문지
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• 제11권7호
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• pp.659-664
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• 2016

본 논문에서는 고속 동작과 저전력 동작을 요구하는 디지털 회로 시스템에 사용될 수 있는 Current-mode FIR Filter를 위한 OTA(:Operational Trans-conductance Amplifier) 회로를 제안한다. Current-mode 신호처리는 동작 주파수와 상관없이 일정한 전력을 유지하는 특징이 있기 때문에 고속 동작을 요구하는 디지털 회로 시스템의 저전력 동작에 매우 유용한 회로설계 기술이라고 할 수 있다. 0.35um CMOS 공정을 이용한 시뮬레이션 결과, Vdd=2V에서 전원 전압의 50%에 해당하는 약 1V의 Dynamic Range를 확보하였으며, 약 0~200uA의 출력전류를 확인하였다. 설계한 OTA 회로의 전력은 약 21uW가 계산되었으며, Active Layout 면적은 $71um{\times}166um$ 사이즈로 집적화에 유리할 것으로 기대된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2682-2684
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• 1999

This paper presents design and stability analysis of the constant frequency Flyback type converter using average current-mode control. The average current-mode control has been recently reported, and superior characteristics over a peak current-mode control such as a good tracking performance of an average current, no slope compensation and noise immunity. By the improvement of PM(Phase Margin) obt from applying the compensator in the current loop, the stability of designed flyback convert more improved. The validity of designed convert confirmed by simulation and experimental result

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.267-270
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• 2003

This paper proposes high performance $8{\times}8$ multiplier using current-mode quaternary logic technique. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion), current-mode quaternary logic full-adder block, quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. Also, this multiplier can easily adapted to binary system by the encoder, the decoder. This circuit is simulated under 0.35um standard CMOS technology, 5uA unit current, and 3.3V supply voltage using Hspice.

• Journal of Power Electronics
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• 제15권3호
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• pp.712-720
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• 2015

A model predictive current control (MPCC) method that does not employ a cost function is proposed. The MPCC method can decrease common-mode voltages in loads fed by three-phase voltage-source inverters. Only non-zero-voltage vectors are considered as finite control elements to regulate load currents and decrease common-mode voltages. Furthermore, the three-phase future reference voltage vector is calculated on the basis of an inverse dynamics model, and the location of the one-step future voltage vector is determined at every sampling period. Given this location, a non-zero optimal future voltage vector is directly determined without repeatedly calculating the cost values obtained by each voltage vector through a cost function. Without utilizing the zero-voltage vectors, the proposed MPCC method can restrict the common-mode voltage within ± V_dc/6, whereas the common-mode voltages of the conventional MPCC method vary within ± V_dc/2. The performance of the proposed method with the reduced common-mode voltage and no cost function is evaluated in terms of the total harmonic distortions and current errors of the load currents. Simulation and experimental results are presented to verify the effectiveness of the proposed method operated without a cost function, which can reduce the common-mode voltage.