• Journal of information and communication convergence engineering
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• 제8권5호
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• pp.566-569
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• 2010

This paper describes the sinusoidal, pulse, triangular oscillator using second generation current conveyor. To obtain the sinusoidal waveform the circuit blocks are constructed by using all pass filter and integrator. The pulse and the triangular waveforms are obtained from the output of sinusoidal oscillator. The peak-to-peak voltages of sinusoidal and triangular waveforms can be easily controlled by the dc offset voltage. Also the output frequency of the oscillator can be controlled by varying passive elements. The designed circuit is verified by HSPICE simulation.

• Journal of Multimedia Information System
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• 제5권2호
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• International journal of advanced smart convergence
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• 제10권1호
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• IEIE Transactions on Smart Processing and Computing
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• 제3권6호
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• pp.404-409
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• 2014

This paper presents a Spread Spectrum Clock Generator (SSCG) based on Relaxation oscillator using Up/Down Counter. The current is controlled by a counter and the spread spectrum of the Relaxation Oscillator. A Relaxation Oscillator with temperature compensation using the BGR and ADC is presented. The current to determine the frequency of the Relaxation Oscillator can be controlled. The output frequency of the temperature can be compensated by adjusting the current according to the temperature using the code that is the output from the ADC and BGR. EMI Reduction of SSCG is 11 dB, and Spread down frequency is 150 kHz. The current consumption is $600{\mu}A$ from 5V and the operating frequency is from 2.3 MHz to 5.75 MHz. The rate of change of the output frequency with temperature was approximately ${\pm}1%$. The SSCG is fabricated in a 0.35um CMOS process with active area $250um{\times}440um$.

• 전기학회논문지
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• 제59권12호
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• pp.2273-2277
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• 2010

In this paper a 2.4GHz CMOS colpitts type microwave oscillator was designed and fabricated using H-spice and Cadence Spetre. There are 140MHz difference between the oscillation frequency and the resonance frequency of a tank circuit of the designed oscillator. The difference is seemed to be due to the parasitic component of the transistor. The inductors used in this design are the spiral inductors proposed in other papers. Cascode current source was used as a bias circuit of a oscillator and the output transistor of the current source is used as the oscillation transistor. A common drain buffer amplifier was used at the output of the oscillator. The measured oscillation frequency and output power of the oscillator are 2.173GHz and -5.53dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.484-494
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• 2014

We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ${\pm}2.6%$ at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively.

• 한국산업정보학회논문지
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• 제18권5호
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• pp.39-44
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• 2013

본 논문에서는 BGR과 ADC를 사용하여 Temperature Compensation 기능을 가진 Relaxation Oscillator를 제안한다. Relaxation Oscillator는 전류조절을 통해 주파수를 결정한다. 제안하는 Relaxation Oscillator는 온도에 따른 출력 주파수를 보상하기 위하여 온도에 따른 ADC 및 BGR의 출력 코드를 사용하여 전류를 조절한다. 제안하는 Relaxation Oscillator는 CMOS 0.35 ${\mu}m$ 공정으로 설계되었으며, 면적은 $240{\mu}m{\times}210{\mu}m$ 이다. 전류 소모는 공급전압인 5 V에서 600 ${\mu}A$이며, 온도에 대한 출력 주파수는 ${\pm}1%$이내의 정확도를 가진다.

• 전기전자학회논문지
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• 제19권4호
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• pp.465-471
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• 2015

An LC-tuned sinusoidal voltage-controlled oscillator (VCO) using temperature-stable linear operational transconductance amplifiers (OTAs) is presented. Its architecture is based on Hartley oscillator configuration, where the inductor is active one realized with two OTAs and a grounded capacitor. Two diode limiters are used for limiting amplitude. A prototype oscillator built with discrete components exhibits less than 3.1% nonlinearity in its current-to-frequency transfer characteristic from 1.99 MHz to 39.14 MHz and $220ppm/^{\circ}C$ frequency stability to the temperature drift over 0 to $75^{\circ}C$. The total harmonic distortion (THD) is as low as 4.4 % for a specified frequency-tuning range. The simulated phase noise of the VCO is about -108.9 dBc/Hz at 1 MHz offset frequency in frequency range of 0.4 - 46.97 MHz and property of phase noise of VCO is better than colpitts-VCO.

• 전기전자학회논문지
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• 제12권3호
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• pp.167-171
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• 2008

저항형 센서 브리지를 인터페이싱 하기 위한 저항 편차-주파수 변환기를 제시하였다. 이 변환기는 선형 연산 트랜스컨덕턴스 증폭기(linear operational transconductance amplifier: LOTA)와 전류-제어 발진기(current-controlled oscillator: CCO)로 구성된다. 제시된 변환기를 상업용 개별 소자들을 이용하여 SPICE 시뮬레이션 하였다. 시뮬레이션 결과는, 변환기가 16.90 kHz/${\Omega}$의 변환 감도와 ${\pm}$0.03 %의 최대 선형 오차를 가진다는 것을 보여준다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.42-47
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• 2017

This paper proposes a new series-coupled voltage-controlled oscillator (VCO). The proposed VCO consists of four current-reuse Armstrong VCOs (CRA-VCOs) coupled by four transformers. The series-coupling, current-reuse, and Armstrong topologies improve the phase noise performance by increasing the negative-Gm of the VCO core with half the current consumption of a conventional differential VCO. The proposed VCO consumes 6.54 mW at 9.78 GHz from a 1-V supply voltage. The measured phase noise is -115.1 dBc/Hz at an offset frequency of 1 MHz, and the FoM is -186.5 dBc/Hz. The frequency tuning range is from 9.38-10.52 GHz. The core area is $0.49mm^2$ in a $0.13-{\mu}m$ CMOS process.