• Title/Summary/Keyword: Current-Reused Topology

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Design of a Low Power Capacitor Cross-Coupled Common-Gate Low Noise Amplifier (캐패시터 크로스 커플링 방법을 이용한 5.2 GHz 대역에서의 저전력 저잡음 증폭기 설계)

  • Shim, Jae-Min;Jeong, Ji-Chai
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.3
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    • pp.361-366
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    • 2012
  • This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

Design of Low Power CMOS LNA for 2.4 GHz ZigBee Applications (2.4 GHz ZigBee 응용을 위한 저전력 CMOS LNA 설계)

  • Cho In-Shin;Yeom Kee-Soo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.259-262
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    • 2006
  • This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications. The proposed circuit has been designed by using TSMC $0.18{\mu}m$ CMOS process and current-reused two-stage cascade topology. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results shows that the LNA has a extremely low power dissipation of 1.38mW with a $V_{DD}$ of 1.0V. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and noise figure of 1.13dB.

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Design of Low Noise Amplifier Utilizing Input and Inter Stage Matching Circuits (다양한 매칭 회로들을 활용한 저잡음 증폭기 설계 연구)

  • Jo, Sung-Hun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.6
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    • pp.853-856
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    • 2021
  • In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

Design of UWB CMOS Low Noise Amplifier Using Inductor Peaking Technique (인덕터 피킹기법을 이용한 초광대역 CMOS 저잡음 증폭기 설계)

  • Sung, Young-Kyu;Yoon, Kyung-Sik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.1
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    • pp.158-165
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    • 2013
  • In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

Design of Low Power CMOS LNA for using Current Reuse Technique (전류 재사용 기법을 이용한 저전력 CMOS LNA 설계)

  • Cho In-Shin;Yeom Kee-Soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.8
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    • pp.1465-1470
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    • 2006
  • This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC $0.18{\mu}m$ CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.