• International Journal of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.29-34
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• 2017

Over the past several decades, embedded system and flight control computer technologies have been evolved to meet the diverse needs of the mobile device market. Current embedded systems are at the heart of technologies that can take advantage of small-sized specialized hardware while still providing high-efficiency performance at low cost. One of these key technologies is multiple memory banks. For example, a dual memory bank can provide two times more memory bandwidth in the same memory space. This benefit take lower cost to provide the same bandwidth. However, there is still few software technologies to support the efficient use of multiple memory banks. In this study, we present a technique to efficiently exploit multiple memory banks by software support. Specifically, our technique use an interference graph to optimally allocate data to different memory banks by an optimizing compiler. As a result, the execution time can be improved upto 7% with the proposed technique.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.281-284
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• 2004

Photo-induced memory effect of an organic light-emitting diode(OLED) composed of a hydrazone-derivative(DBAH) dispersed in bis-phenol-A type polycarbonate polymer(PCA) in the presence of thio-Michler's ketone, was investigated by the measuring of the current density and luminance at the various conditions. After the light exposure, the current of the OLED was decreased approximately one order, and the luminance of the OLED also decresed. This memory effct was erasable by heating the OLED to the temperature higher than the glass transition temperature(Tg). As shown in this result, we found the memory effect was erased by heating and returned to its original state in the hole injecting layer(HIL) of the OLED. A series of these phenomena was suggested the possibility of the application to the imaging plate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.44-47
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• 1991

Electron injection and memory retention chracteristics of the MNOS devices with thin oxide layer of 23${\AA}$ thick and silicon nitride layer of 1000${\AA}$ thick which are fabricated for this experiment. As a result, pulse amplitude increase oxide current is dominated in linearly increasing region of $\Delta$V$\_$FB/the decreasing region after saturation was due to the increased silicon nirtide current. In low pulse ampiltude $\Delta$V$\_$FB/ is not variated on temperature, but as temperature and pulse amplitude increase. $\Delta$V$\_$FB/ is decreased after saturation. And the decay rate during 10$^4$sec after electron injection was ohiefly dominated by the back tunneling of emission from memory trap to silicon. Memory retention characteristics in V$\_$FB/ stage was better than that of OV retention regardless of injection conditions.

• Smart Structures and Systems
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• v.14 no.4
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• pp.541-558
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• 2014

This paper proposes a new design of shape memory alloy (SMA) wire actuated gripper for open mode operation. SMA can generate smooth muscle movements during actuation which make them potentially good contenders in designing grippers. The principle of the shape memory alloy gripper is to convert the linear displacement of the SMA wire actuator into the angular displacement of the gripping jaw. Steady state analysis is performed to design the wire diameter of the bias spring for a known SMA wire. The gripper is designed to open about an angle of $22.5^{\circ}$ when actuated using pulsating electric current from a constant current source. The safe operating power range of the gripper is determined and verified theoretically. Experimental evaluation for the uncontrolled gripper showed a rotation of $19.97^{\circ}$. Forced cooling techniques were employed to speed up the cooling process. The gripper is simple and robust in design (single movable jaw), easy to fabricate, low cost, and exhibits wide handling capabilities like longer object handling time and handling wide sizes of objects with minimum utilization of power since power is required only to grasp and release operations.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.12
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• pp.759-763
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• 2016

We demonstrate the utilization of ion gel gate dielectrics for operating non-volatile transistor memory devices based on polymer semiconductor thin films. The gating process in typical electrolyte-gated polymer transistors occurs upon the penetration and escape of ionic components into the active channel layer, which dopes and dedopes the polymer film, respectively. Therefore, by controlling doping and dedoping processes, electrical current signals through the polymer film can be memorized and erased over a period of time, which constitutes the transistor-type memory devices. It was found that increasing the thickness of polymer films can enhance the memory performance of device including (i) the current signal ratio between its memorized state and erased state and (ii) the retention time of the signal.

• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• International Journal of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.185-196
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• 2002

MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

• 한국노년학
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• v.28 no.4
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• pp.925-940
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• 2008

As the proportion of old people in contemporary societies steadily increases, the influence on cognitive rehabilitation strategy of the memory deficit associated with normal and pathological aging grows greater as well. This paper reviewed the current memory rehabilitation techniques for older adults. In the first part of this article, human memory systems as a framework for understanding memory aging were considered. In the second part, research findings concerning memory performance in normal aging and Alzheimer's disease were reviewed. Finally, recent evidence for the kinds of memory rehabilitation procedures with proven efficacy were offered. The existent memory rehabilitation technique have focused on prompt of residual explicit memory, use of preserved implicit memory, utilization of memory external memory aids. A suggestion of memory training based on brain plasticity as a novel approach is offered.