• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• Journal of Power Electronics
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• v.7 no.4
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• pp.310-317
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• 2007

In this paper, an analysis and hysteretic controller design of a $3^{rd}$ order buck converter is presented. The proposed hysteretic controller consists of an inner current-loop, just like the conventional cascade control scheme, and an outer voltage-loop for load voltage regulation. Although it is possible to include an inner current loop from different branches of the converter, from the feasibility and operational point of view, the load side capacitor current would be the better choice. The addition of an inner current-loop improves the dynamic performance of the converter while preserving the robustness of the hysteretic control. The controller formulation and closed-loop converter performance analysis are validated through computer simulations. Few experimental results of the proposed converter are given and compared with the buck converter.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.3
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• pp.111-115
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• 2015

Recently, protection coordination issues can occur due to increased fault current in power system when power system being changed radial power system to grid system such as loop power system, micro grid and smart grid. This paper analyzed Recloser-Fuse coordination in loop power distribution system with Superconducting Fault Current Limiters(SFCLs) when single line ground fault occur in loop power distribution system with SFCLs. We analyzed Recloser-Fuse Coordination in radial power distribution system and changed coordination caused by increased Fault current because of loop system when single line ground fault occur in power distribution system. This paper simulated to improve changed coordination using SFCLs in loop power distribution system. Power distribution system, SFCLs and protective devices are modeled using PSCAD/EMTDC.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.7
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• pp.634-640
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• 2011

When a servo position controller of a robot or a driving units is composed of a PID controller, servomechanism which is modelled is composed of current, velocity and position control loops. After this model is simulated, the technique operating gain of each controller is suggested. The model consists of current, velocity and position controllers from the inside to the outside gradually. Also, to combine velocity and position controllers with 2 order system, simulation is performed after current controllers are composed, which are able for current loop to work ideally. If a current controller is treated with constant, it is possible for velocity and position controller to consist of controller into 2 order system. The technique is verified by applying T-company servo motor which is much more applied to current, velocity and position controller robots.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.5
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• pp.278-286
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• 2000

A new large-scale network geometric analysis is introduced. For a large-scale circuit, it must be analyzed with a geometric diagram and figure. So many equations are induced from a geometric loop-node diagram. The results are arranged into a simple matrix, of course. In case of constructing a network diagram, it is not easy to handle voltage and current sources together. Geometric loop analysis is related to voltage sources, and node analysis is to current sources. The reciprocal transfer is possible only to have series or parallel impedance. If not having this impedance, in order to obtain equivalent circuit, many equations must be derived. In this paper a loop-reduction method is proposed. With this method current source branch is included into the other branch, and disappears in circuit diagram. So the number of independent circuit equations are reduced as much as that of current sources. The number is not (b-n+1), but (b-n+1-p). Where p is the number of current sources. The reduction procedure is verified with a geometric principle and circuit theory. A resultant matrix can be constructed directly from this diagram structure, not deriving circuit equations. We will obtain the last results with the help of a computer.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.136-141
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.609-614
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• 1998

A new small signal modeling of an average current mode control is proposed. In order to analyze the characteristics of the control scheme, the discrete and continuous time small signal models are derived. The derivation are mainly come from the analysis of the sampling effect presented in the current control loop. By the mathematical interpretation of practical sampler representing the sampling effect of a current control loop, the small signal models of an average current mode control can be easily derived. The instability of the current control loop, which gives rise to the subharmonic oscillation, can be identified by the proposed models. To show the usefulness of the proposed models, the simulation and experiment are carried out. The results show that the predicted results by the proposed model are much better agreed with the measured ones than that of the conventional model, even though the high gain of the compensation network of a current control loop is employed.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1632-1633
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• 2007

This paper presents a new method of designing digital controller based on closed-loop identification of a pulse width modulation (PWM) converter system. We consider the control system structure which is composed of both current control loop and voltage control loop. The current controller can be designed independently of voltage loop. Whereas voltage controller can not do easily due to the PWM switching component which is nonlinear in nature. Furthermore, the control objective of inner loop is to track the sine wave of 60 Hz, but the outer loop shall maintain the constant DC voltage irrespective to load change. To systematically design outer loop controller, we propose a method finding linear approximate model of the nonlinear inner loop part including current controller by closed loop identification. Based on the identified model, we show that a simple digital voltage controller can be directly designed and it has good performance.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.1970-1979
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• 2017

Ultra Lift Luo Converter (ULC) gained considerable research interest in recent years. The stability analysis of voltage mode and peak current mode controlled ULC in continuous conduction mode is analyzed in this paper. The Eigen value theory is used for the stability analysis of voltage mode controlled ULC. Then to characterize the dynamics of inner current loop, the expressions of closed loop transfer function and loop gain are determined. An algorithm has been developed to analyze the stability of the peak current mode controlled ULC. The theoretical results are correlated with the simulation results obtained using PSIM 9.1(SMARTCTRL 1.0) software. Finally it is proposed to fabricate a prototype and validate the performance by suitable experimental setup.