• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.62-62
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• 2008

As micro-system move toward higher speed and miniaturization, requirements for embedding the passive components into printed circuit boards (PCBs) grow consistently. They should be fabricated in smaller size with maintaining and even improving the overall performance. Miniaturization potential steps from the replacement of surface-mount components and the subsequent reduction of the required wiring-board real estate. Among the embedded passive components, capacitors are most widely studied because they are the major components in terms of size and number. Embedding of passive components such as capacitors into polymer-based PCB is becoming an important strategy for electronics miniaturization, device reliability, and manufacturing cost reduction Now days, the dielectric films deposited directly on the polymer substrate are also studied widely. The processing temperature below $200^{\circ}C$ is required for polymer substrates. For a low temperature deposition, bismuth-based pyrochlore materials are known as promising candidate for capacitor $B_2Mg_{2/3}Nb_{4/3}O_7$ ($B_2MN$) multi layers were deposited on Pt/$TiO_2/SiO_2$/Si substrates by radio frequency magnetron sputtering system at room temperature. The physical and structural properties of them are investigated by SEM, AFM, TEM, XPS. The dielectric properties of MIM structured capacitors were evaluated by impedance analyzer (Agilent HP4194A). The leakage current characteristics of MIM structured capacitor were measured by semiconductor parameter analysis (Agilent HP4145B). 200 nm-thick $B_2MN$ muti layer were deposited at room temperature had capacitance density about $1{\mu}F/cm^2$ at 100kHz, dissipation factor of < 1% and dielectric constant of > 100 at 100kHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.169-169
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• 2008

To keep pace with scaling trends of CMOS technologies, high-k metal oxides are to be introduced. Due to their high permittivity, high-k materials can achieve the required capacitance with stacks of higher physical thickness to reduce the leakage current through the scaled gate oxide, which make it become much more promising materials to instead of $SiO_2$. As further studying on high-k, an understanding of the relation between the etch characteristics of high-k dielectric materials and plasma properties is required for the low damaged removal process to match standard processing procedure. There are some reports on the dry etching of different high-k materials in ICP and ECR plasma with various plasma parameters, such as different gas combinations ($Cl_2$, $Cl_2/BCl_3$, $Cl_2$/Ar, $SF_6$/Ar, and $CH_4/H_2$/Ar etc). Understanding of the complex behavior of particles at surfaces requires detailed knowledge of both macroscopic and microscopic processes that take place; also certain processes depend critically on temperature and gas pressure. The choice of $BCl_3$ as the chemically active gas results from the fact that it is widely used for the etching o the materials covered by the native oxides due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. In this study, the surface reactions and the etch rate of $Al_2O_3$ films in $BCl_3/Cl_2$/Ar plasma were investigated in an inductively coupled plasma(ICP) reactor in terms of the gas mixing ratio, RF power, DC bias and chamber pressure. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by AFM and SEM. The chemical states of film was investigated using X-ray photoelectron spectroscopy (XPS), which confirmed the existence of nonvolatile etch byproducts.

• Journal of IKEEE
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• v.17 no.1
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• pp.71-76
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• 2013

AlGaN/GaN HEMTs (High electron mobility transistors) with narrow channel were fabricated and the effect of channel scaling on the device were investigated. The devices were fabricated using e-beam lithography to have same channel length of $1{\mu}m$ and various channel width from 0.5 to $9{\mu}m$. The sheet resistance of the channel was increased corresponding to the decrease of channel width and the increase was larger at the width of sub-${\mu}m$. The threshold voltage of the HEMT with $1.6{\mu}m$ and $9{\mu}m$ channel width was -2.85 V. The transistor showed a variation of 50 mV at the width of $0.9{\mu}m$ and the variation 350 mV at $0.5{\mu}m$. The transconductance of 250 mS/mm was decreased to 150 mS/mm corresponding to the decrease of channel width. Also, the gate leakage current of the HEMT decreased with channel width. But the degree of was reduced at the width of sub-${\mu}m$. It was thought that the variation of the electrical characteristics of the HEMT corresponding to the channel width came from the reduced Piezoelectric field of the AlGaN/GaN structure by the strain relief.

• Korean Journal of Materials Research
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• v.18 no.4
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• pp.169-174
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• 2008

The structural and electrical properties of amorphous $BaSm_2Ti_4O_{12}$ (BSmT) films on a $TiN/SiO_2/Si$ substrate deposited using a RF magnetron sputtering method were investigated. The deposition of BSmT films was carried out at $300^{\circ}C$ in a mixed oxygen and argon ($O_2$ : Ar = 1 : 4) atmosphere with a total pressure of 8.0 mTorr. In particular, a 45 nm-thick amorphous BSmT film exhibited a high capacitance density and low dissipation factor of $7.60\;fF/{\mu}m2$ and 1.3%, respectively, with a dielectric constant of 38 at 100 kHz. Its capacitance showed very little change, even in GHz ranges from 1.0 GHz to 6.0 GHz. The quality factor of the BSmT film was as high as 67 at 6 GHz. The leakage current density of the BSmT film was also very low, at approximately $5.11\;nA/cm^2$ at 2 V; its conduction mechanism was explained by the the Poole-Frenkel emission. The quadratic voltage coefficient of capacitance of the BSmT film was approximately $698\;ppm/V^2$, which is higher than the required value (<$100\;ppm/V^2$) for RF application. This could be reduced by improving the process condition. The temperature coefficient of capacitance of the film was low at nearly $296\;ppm/^{\circ}C$ at 100 kHz. Therefore, amorphous BSmT grown on a TiN substrate is a viable candidate material for a metal-insulator-metal capacitor.

• Korean Chemical Engineering Research
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• v.51 no.3
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• pp.308-312
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• 2013

Active carbons with high specific surface area and micro pore structure were prepared from the coconut shell char using the chemical activation method of NaOH. The preparation process has been optimized through the analysis of experimental variables such as activating chemical agents to char ratio and the flow rate of gas during carbonization. The active carbons with the surface area (2,481 $m^2/g$) and mean pore size (2.32 nm) were obtained by chemical activation with NaOH. The electrochemical performances of hybrid capacitor were investigated using $LiMn_2O_4$, $LiCoO_2$ as the positive electrode and prepared active carbon as the negative electrode. The electrochemical behaviors of hybrid capacitor using organic electrolytes ($LiPF_6$, $TEABF_4$) were characterized by constant current charge/discharge, cyclic voltammetry, cycle and leakage tests. The hybrid capacitor using $LiMn_2O_4$/AC electrodes had better capacitance than other hybrid systems and was able to deliver a specific energy as high as 131 Wh/kg at a specific power of 1,448 W/kg.

• Journal of the Korean Ceramic Society
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• v.40 no.11
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• pp.1067-1072
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• 2003

The electrical stability of the varistor ceramics composed of Zn-Pr-Co-Cr-Dy oxides-based varistors was investigated at 0.0∼2.0 mol% Dy$_2$O$_3$ content under DC accelerated aging stress. The ceramic density was increased up to 0.5 mol% Dy$_2$O$_3$ whereas further addition of Dy$_2$O$_3$ decreased sintered ceramic density. The density sailently affected the stability due to the variation of conduction path. The nonlinearity of varistor ceramics was greatly improved above 45 in the nonlinear exponent and below nearly 1.0 ${\mu}$A by incorporating Dy$_2$O$_3$. Under 0.95 V$\_$1mA/150$^{\circ}C$/24 h stress state, the varistor ceramics doped with 0.5 mol% Dy$_2$O$_3$ exhibited the highest electrical stability, in which the variation rates of varistor voltage, nonlinear exponent, and leakage current were -0.9%, -14.4%, and +483.3%, respectively. The variation rates of relative permittivity and dissipation factor were +7.1% and +315.4%, respectively. The varistors with further addition of Dy$_2$O$_3$ exhibited very unstable state resulting in the thermal runaway due to low density.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.406-406
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• 2010

일반적으로, 나노스케일의 MOS 소자에서는 게이트 절연체 두께가 감소함에 따라 tunneling effect의 증가로 인해 PID (plasma induced damage)로 인한 소자 특성 저하 현상을 감소하는 추세로 알려져 있다. 하지만 요즘 많이 사용되고 있는 high-k 게이트 절연체의 경우에는 오히려 더 많은 charge들이 trapping 되면서 PID가 오히려 더 심각해지는 현상이 나타나고 있다. 이러한 high-k 게이트 식각 시 현재는 주로 Hf-based wet etch나 dry etch가 사용되고 있지만 gate edge 영역에서 high-k 게이트 절연체의 undercut 현상이나 PID에 의한 소자특성 저하가 보고되고 있다. 본 연구에서는 이에 차세대 MOS 소자의 gate stack 구조중 issue화 되고 있는 metal gate 층과 gate dielectric 층의 식각공정에 각각 중성빔 식각과 중성빔 원자층 식각을 적용하여 전기적 손상 없이 원자레벨의 정확한 식각 조절을 해줄 수 있는 새로운 two step 식각 공정에 대한 연구를 진행하였다. 먼저 TiN metal gate 층의 식각을 위해 HBr과 $Cl_2$ 혼합가스를 사용한 중성빔 식각기술을 적용하여 100 eV 이하의 에너지 조건에서 하부층인 $HfO_2$와 거의 무한대의 식각 선택비를 얻었다. 하지만 100 eV 조건에서는 낮은 에너지에 의한 빔 스케터링으로 실제 패턴 식각시 etch foot이 발생되는 현상이 관찰되었으며, 이를 해결하기 위하여 먼저 높은 에너지로 식각을 진행하고 $HfO_2$와의 계면 근처에서 100 eV로 식각을 해주는 two step 방법을 사용하였다. 그 결과 anistropic 하고 하부층에 etch stop된 식각 형상을 관찰할 수 있었다. 다음으로 3.5nm의 매우 얇은 $HfO_2$ gate dielectric 층의 정확한 식각 깊이 조절을 위해 $BCl_3$와 Ar 가스를 이용한 중성빔 원자층 식각기술을 적용하여 $1.2\;{\AA}$/cycle의 단일막 식각 조건을 확립하고 약 30 cycle 공정시 3.5nm 두께의 $HfO_2$ 층이 완벽히 제거됨을 관찰할 수 있었다. 뿐만 아니라, vertical 한 식각 형상 및 향상된 표면 roughness를 transmission electron microscope(TEM)과 atomic force microscope (AFM)으로 관찰할 수 있었다. 이러한 중성빔 식각과 중성빔 원자층 식각기술이 결합된 새로운 gate recess 공정을 실제 MOSFET 소자에 적용하여 기존 식각 방법으로 제작된 소자 결과를 비교해 본 결과 gate leakage current가 약 one order 정도 개선되었음을 확인할 수 있었다.

• Korean Journal of Materials Research
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• v.2 no.5
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• pp.353-359
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• 1992

Thermal oxidation and plasma enhanced chemical vapor deposition of tantalum oxide thin films on p-type (100) Si substrates were studied to examine the dielectric nature of T$a_2O_5$ as a Al/T$a_2O_5$/p-Si capacitor. Microstructure and dielectric properties of the capacitors were investigated by XRD, AES, high frequency C-V analyzer, I-V meter and TEM. XRD analysis showed that the structure of T$a_2O_5$ films were amorphous, but the films were crystallized to hexagonal $\delta$-T$a_2O_5$ by 65$0^{\circ}C$ thermal oxidation treatment. It was found that the stoichiometry of the films was more or less close to 2 : 5. Leakage current density and relative dielectric constant of thermal oxidation T$a_2O_5$ film at 60$0^{\circ}C$ was 5.0${ imes}10^{-6}$/A/c$m^2 and 31.5, respectively. In the case of PECVD T$a_2O_5$film deposited at 0.47W/c$m^2 they were 2.5${ imes}10^{-5}$/A/$ extrm{cm}^2$ and 24.0, respectively. The morphology of the films and interfaces were investigated by TEM.

• Journal of the Korea Institute of Construction Safety
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• v.1 no.1
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• pp.31-39
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• 2018

It is reported that about 20 % of all fires in Korea are caused by the electric equipment and installations. In complex and large-scale buildings, the sizes of electric fires are becoming larger as property damage and casualties increase. Among the causes of various electric fires, fire by short circuit accounts for about 71.5% of overall fires, and in the classification by electric equipment and installation, fire caused by wiring and wiring equipment accounts for approximately 38.3% of overall fires. The purpose of this study is to propose methods to prevent electric fires due to short circuit by improving indoor wiring currently in use and to find the fundamental measures to prevent wiring equipment caused fires by improving the socket and plug which are commonly used in wiring equipment. It is expected that the electric fire prevention measures presented through this study can be used as a measure to protect many people and properties by eliminating the root cause of electric fire.

• Journal of IKEEE
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• v.22 no.4
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• pp.1226-1229
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• 2018

We investigated the improvement of surface roughness and states after high temperature annealing using reduced-graphene oxide (r-GO) capping layer on ion-implanted 4H-SiC epitaxial layer. The specification of the 4H-SiC wafer grown on n-type $4^{\circ}$ off-axis 4H-SiC was $10{\mu}m$-thick and n-type epitaxial layer with a dose of $1.73{\times}10^{15}cm^{-2}$. The $n^+$ region were formed by multiple nitrogen ion-implantations and r-GO capping layer was produced by spray coating method. AFM measurements revealed that RMS value of the sample capped with r-GO was tenfold decrease compared to the sample without r-GO capping. The improvement of surface states was also verified by the improvement of leakage current level.