• 한국정밀공학회지
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• 제17권10호
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• pp.69-76
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• 2000

Lots of semi-active control devices have been developed in recent years because they have the best features of passive and active system. Especially, controllable magneto-rheological(MR) fluid devices have received significant attention in these area of research. The MR fluid is the material that reversibly changes from a free-flowing, linear viscous fluid to a semisolid with a controllable yield strength in milliseconds when exposed to a magnetic field. If the magnetic field is induced by moving a permanent magnet instead of applying current to a solenoid, it is possible to design a MR damper consuming low power because the power consumption is reduced at steady state. This paper proposes valve mode MR damper using permanent magnetic circuit that has wide range of operation with low power consumption, a design parameter is adopted. The magnetic circuit, material of choke and choke type are selected experimentally with the design parameter. The behaviors of the damper are examined and torque tracking control using PID feedback controller is performed for step, ramp and sinusoidal trajectiories.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.477-477
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• 2009

Bimodal Tram developed by KRRI is driven by a series Hybrid propulsion system which has both the CNG engine, generator and LPB(Lithium Polymer Battery) pack. It has three driving modes; Hybrid mode, Engine mode and Battery mode. Even in case of Battery mode, LPB pack to get enough power to drive the vehicle only by itself onsists of 168 LPB cells(80Ah per lcell), 650V. It is important thing to manage LPB pack in a right way, which will extend the lifetime of LPB cells and operate in the hybrid mode effectively. This paper has shown the development of battery management system(12 BMS, 1 BMS per 14cells) to manage LPB pack which is connected with CAN(Controller Area Network) each other and measure the voltage, current, temperature and also control the cooling fan inside of LPB pack. Using the measured data, BMS can show the SOC(State of Charge), SOH(State of Health) and other status of LPB pack including of the cell balancing.

• 전기학회논문지P
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• 제64권4호
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• pp.231-235
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• 2015

Bimodal Tram developed by KRRI is driven by a series Hybrid propulsion system which has both the CNG engine, generator and LPB(Lithium Polymer Battery) pack. It has three driving modes; Hybrid mode, Engine mode and Battery mode. Even in case of Battery mode, LPB pack to get enough power to drive the vehicle only by itself onsists of 168 LPB cells(80Ah per lcell), 650V. It is important thing to manage LPB pack in a right way, which will extend the lifetime of LPB cells and operate in the hybrid mode effectively. This paper has shown the development of battery management system(12 BMS, 1 BMS per 14cells) to manage LPB pack which is connected with CAN(Controller Area Network) each other and measure the voltage, current, temperature and also control the cooling fan inside of LPB pack. Using the measured data, BMS can show the SOC(State of Charge), SOH(State of Health) and other status of LPB pack including of the cell balancing.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.445-453
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• 2015

A fully integrated cost-effective and low-power single chip Lithium-Ion (Li-Ion) battery protection IC (BPIC) for portable devices is presented. The control unit of the battery protection system and the MOSFET switches are integrated in a single package to protect the battery from over-charge, over-discharge, and over-current. The proposed BPIC enters into low-power standby mode when the battery becomes over-discharged. A new auto release function (ARF) is adopted to release the BPIC from standby mode and safely return it to normal operation mode. A new delay shorten mode (DSM) is also proposed to reduce the test time without increasing pin counts. The BPIC implemented in a $0.18-{\mu}m$ CMOS process occupies an area of $750{\mu}m{\times}610{\mu}m$. With DSM enabled, the measured test time is dramatically reduced from 56.82 s to 0.15 s. The BPIC chip consumes $3{\mu}A$ under normal operating conditions and $0.45{\mu}A$ under standby mode.

• 한국자동차공학회논문집
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• 제22권4호
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• pp.89-97
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• 2014

As the digital control technologies in automotive industry have advanced, electronic control units(ECUs) play a key-role to improve system performance. Transmission control unit(TCU) is a shifting controller for automatic transmission of which major functions are to determine the shift and manage the shifting process considering the various sensor signal on transmission and driver's commands. As with any ECU in vehicle, TCU performs complex algorithms such as shift control, diagnostic and failsafe functions. However, firmware design analysis is hardly possible by the reverse engineering due to code protection. Transmission simulator is a hardware-in-the-loop simulator which enables TCU to work in normal mode by simulating the electrical signal of TCU interface. In this research, diagnosis and failsafe algorithm implemented on commercialized TCU is analyzed by using the transmission simulator that is developed for wheel loader construction vehicle. This paper gives various experimental results on the proportional solenoid current trajectories for different operating modes, error detection criterion and limphome mode gears for all the possible cases of clutch malfunction. The derived results for conventional TCU can be applied to the development of inherent TCU algorithms and the transmission simulator can also be utilized for the test of TCU to be developed.

• 조명전기설비학회논문지
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• 제21권6호
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• pp.33-39
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• 2007

본 논문은 부하에 대한 빠른 응답 특성을 보이는 새로운 SRM 구동 토폴로지를 제안하였다. PI 제어기 출력이 포화될 때 windup 현상이 나타나고 그 결과로 성능이 저하된다. 따라서 전동기의 가변속 제어 성능을 위해 가속 시에는 개선된 Anti-Windup PI 제어기만을 사용하고 감소 시에는 추가로 부하의 특성을 고려하여 braking 동작을 사용하였다. 시뮬레이션 및 실험 결과는 속도 성능면에서 제안된 방식이 종래의 다른 제어 방식에 비해 우수함을 보여 준다.

• 융합신호처리학회논문지
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• 제4권2호
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• pp.61-69
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• 2003

본 논문에서는 반도체 소자의 DC 파라메터에 대한 특성을 검사하는 DC 파라메터 검사 시스템을 개발하였다. 개발된 시스템은 IBM-PC와 연결하기 위한 CPLD(Complex Programmable Logic Device)로 구현된 연결부와 ADC/DAC부, 전압원/전류원, 가변저항부, 측정부로 구성되어 있다. 제안된 시스템에서 정전압원과 정전류원은 하나의 회로로 설계하여 외부의 컴퓨터에서 주어지는 모드명령에 의해 선택되도록 하였으며, VHDL(VHSIC Hardware Description Language)을 사용하여 회로를 제어하고 신호를 변환하는 기능을 CPLD로 설계하였다. 제안된 시스템은 두 개의 채널을 가지고 있으며, VFCS(Voltage Force Current Sensing) 모드와 CFVS(Current Force Voltage Sensing) 모드로 동작할 수 있도록 하였다. 검사 전압의 범위는 0(V)-10(V)까지이고, 검사전류의 범위는 0[mA]-100[mA]까지로 다이오드를 사용하여 설계된 회로의 성능을 검증하였다.

• 전기전자학회논문지
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• 제13권2호
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• pp.208-215
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• 2009

본 논문에서는 DT-CMOS(Dynamic Threshold voltage CMOS) 스위칭 소자를 사용한 모바일 기기용 고 효율 전원 제어 장치(PMIC)를 제안하였다. 휴대기기에서 필요한 높은 출력 전압과 낮은 출력 전압을 제공하기 위하여, 부스트 변환기(Boost Converter)와 벅 변환기(Buck Converter)를 원칩(One-chip)으로 구현하였다. 그리고 높은 출력 전류에서 고 전력 효율을 얻기 위하여 PWM(Pulse Width Modulation) 제어 방식을 사용하여 PMIC를 구현하였으며, 낮은 온 저항을 갖는 DT-CMOS를 설계하여 도통 손실을 감소시켰다. Voltage-mode PWM 제어 회로와 낮은 온 저항 스위칭 소자를 사용하여 구현한 부스트 변환기와 벅 변환기는 100mA 출력 전류에서 92.1%와 95%의 효율을 구현하였으며, 1mA이하의 대기모드에서도 높은 효율을 구현하기 위하여 LDO를 설계하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.