• Bulletin of the Korean Chemical Society
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• v.35 no.6
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• pp.1687-1691
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• 2014

This study reports on the synthesis of carbon nanofibers via chemical vapor deposition using Co and Cu as catalysts. In order to investigate the suitability of their catalytic activity for the growth of nanofibers, we prepared catalysts for the synthesis of carbon nanofibers with Cobalt nitrate and Copper nitrate, and found the optimum concentration of each respective catalyst. Then we made them react with Aluminum nitrate and Ammonium Molybdate to form precipitates. The precipitates were dried at a temperature of $110^{\circ}C$ in order to be prepared into catalyst powder. The catalyst was sparsely and thinly spread on a quartz tube boat to grow carbon nanofibers via thermal chemical vapor deposition. The characteristics of the synthesized carbon nanofibers were analyzed through SEM, EDS, XRD, Raman, XPS, and TG/DTA, and the specific surface area was measured via BET. Consequently, the characteristics of the synthesized carbon nanofibers were greatly influenced by the concentration ratio of metal catalysts. In particular, uniform carbon nanofibers of 27 nm in diameter grew when the concentration ratio of Co and Cu was 6:4 at $700^{\circ}C$ of calcination temperature; carbon nanofibers synthesized under such conditions showed the best crystallizability, compared to carbon nanofibers synthesized with metal catalysts under different concentration ratios, and revealed 1.26 high amorphicity as well as $292m^2g^{-1}$ high specific surface area.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Journal of Welding and Joining
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• v.31 no.3
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• pp.11-16
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• 2013

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.

• Bulletin of the Korean Chemical Society
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• v.34 no.1
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• pp.42-48
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• 2013

Potassium N-heterobiaryltrifluoroborates were successfully prepared via a selective Cu-catalyzed C-N coupling reaction. The $BF_3K$ moiety was well tolerated under the reaction conditions involving CuI and dimethyl-ethylenediamine (DMEDA) in the presence of DMSO. The Pd-catalyzed Suzuki-Miyaura cross couplings of potassium N-heterobiaryltrifluoroborates with bromoarenes were studied to prepare the N-heterotriaryl compounds. Moreover, homocoupling, iodination, and hydroxylation of potassium N-heterobiaryltrifluoroborates provided the corresponding products in high yields.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.19-23
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• 2012

Silicon substrate for light emitting diodes (LEDs) has been the tendency of LED packaging for improving power consumption and light output. In this study, a low cost and high throughput Si through via fabrication has been demonstrated using a wet etching process. Both a wet etching only process and a combination of wet etching and dry etching process were evaluated. The silicon substrate with Si through via fabricated by KOH wet etching showed a good electrical resistance (${\sim}5.5{\Omega}$) of Cu interconnection and a suitable thermal resistance (4 K/W) compared to AlN ceramic substrate.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.53-53
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• 2004

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Korean Journal of Metals and Materials
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• v.49 no.11
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• pp.905-909
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• 2011

The formation of front metal contact silicon solar cells is required for low cost, low contact resistance to silicon surfaces. One of the available front metal contacts is Ni/Cu plating, which can be mass produced via asimple and inexpensive process. A selective emitter, meanwhile, involves two different doping levels, with higher doping (${\leq}30{\Omega}/sq$) underneath the grid to achieve good ohmic contact and low doping between the grid in order to minimize the heavy doping effect in the emitter. This study describes the formation of a selective emitter and a nickel silicide seed layer for the front metallization of silicon cells. The contacts were thickened by a plated Ni/Cu two-step metallization process on front contacts. The experimental results showed that the Ni layer via SEM (Scanning Electron Microscopy) and EDX (Energy dispersive X-ray spectroscopy) analyses. Finally, a plated Ni/Cu contact solar cell displayed efficiency of 18.10% on a $2{\times}2cm^2$, Cz wafer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.319-325
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• 2017

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.

• Journal of the Korean institute of surface engineering
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• v.51 no.6
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• pp.360-364
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• 2018

A facile method to fabricate freestanding CuO nanoleaves and CuO nanowires-based films was demonstrated. $Cu(OH)_2$ nanoleaves and nanowires were prepared by a hydrolysis reaction in aqueous solution including pyridine and NaOH with the tailored concentrations at room temperature. The films of freestanding CuO nanoleaves and CuO nanowires can be successfully obtained via the simple vacuum infiltration following a thermal dehydration reaction. The morphologies and crystallinity of the $Cu(OH)_2$ nanoleaves/nanowires and CuO nanoleaves/nanowires were characterized by XRD, SEM, TEM and FT-IR. The films fabricated with freestanding CuO nanoleaves and nanowires in this study may be applicable for building high-efficiency organic binder-free devices, such as gas sensors, batteries, photoelectrodes for water splitting and so on.