• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.11
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• pp.874-878
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• 2001

Solder bump was electroplated on wafer for flip chip application. The process is as follows. Ti/Cu were sputtered and thick PR was formed by several coating PR layer. Fine pitch vias were opened using via mask and then Cu stud and solder bump were electroplated. Finally solder bump was formed by reflow process. In this paper, we opened 40㎛ vias on 57㎛ thick PR layer and electroplated solder bump with 70㎛ height and 40㎛ diameter. After reflow process, we could form solder bump with 53㎛ height and 43㎛ diameter. In plating process, we improved the plating uniformity within 3% by using ring contact instead of conventional multi-point contact.

• Journal of Sensor Science and Technology
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• v.22 no.1
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• pp.89-94
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• 2013

In this paper, we developed a beam of MEMS probe card using a BeCu sheet. Silicon wafer thickness of $400{\mu}m$ was fabricated by using deep reactive ion etching (RIE) process. After forming through silicon via (TSV), the silicon wafer was bonded with BeCu sheet by soldering process. We made BeCu beam stress-free owing to removing internal stress by using joule heating. BeCu beam was fused by using joule heating caused by high current. The fabricated BeCu beam measured length of 1.75 mm and width of 0.44 mm, and thickness of $15{\mu}m$. We measured fusing current as a function of the cutting planes. Maximum current was 5.98 A at cutting plane of $150{\mu}m^2$. The proposed low-cost and simple fabrication process is applicable for producing MEMS probe beam.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1120-1127
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• 2013

In this paper, novel chip-on-chip(CoC) flip-chip bump structures using chip-on-wafer(CoW) process technology are proposed, designed and fabricated, and their microwave frequency responses are analyzed. With conventional bumps of Cu pillar/SnAg and Cu pillar/Ni/SnAg and novel Polybenzoxazole(PBO)-passivated bumps of Cu pillar/SnAg, Cu pillar/Ni/SnAg and SnAg with the deposition option of $2^{nd}$ Polyimide(PI2) layer on the wafer, 10 kinds of CoC samples are designed and their frequency responses up to 20 GHz are investigated. The measurement results show that the bumps on the wafers with PI2 layers are better for the batch flip-chip process and have average insertion loss of 0.14 dB at 18 GHz. The developed bump structures for chips with fine-pitch pads show similar or slightly better insertion loss of 0.11~0.14 dB up to 18 GHz, compared with that of 0.13~0.17 dB of conventional bump structures in this study, and we find that they could be utilized in various microwave packages for high integration density.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1880-1884
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• 2008

Cleaning is required following CMP (chemical mechanical planarization) to remove particles. The minimization of particle residue is required with each successive technology generation, and the cleaning of wafers becomes more complicated. In copper damascene process for interconnection structure, it utilizes 2-steop CMP consists of Cu CMP and barrier CMP. Such a 2-steps CMP process leaves a lot of abrasive particles on the wafer surface, cleaning is required to remove abrasive particles. In this study, the buffing is performed various conditions as a cleaning process. The buffing process combined mechanical cleaning by friction between a wafer and a buffing pad and chemical cleaning by buffing solution consists of tetramethyl ammonium hydroxide (TMAH)/benzotriazole(BTA).

• Journal of the Korean Chemical Society
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• v.44 no.3
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• pp.200-206
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• 2000

The metal impurities in specific regions at near surface of silicon wafer were determined by constant depth etching·lt is possible to etch uniformly over the entire wafer surface by 1$\mu\textrm{m}$ depth with 5 mL of etching solution made up of HF and HNO$_3$ mixed by l:3 volume ratio. The microwave oven was used to evaporate the solution after etching. After spiking, The recoveries of Cu, Ni, Zn, Cr, Mg and K were found to be 99∼105%ted in polysilicon region and could be quantified by 1$\mu\textrm{m}$ depth.

• Journal of the Korean Vacuum Society
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• v.4 no.S2
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• pp.115-130
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• 1995

In order to produce Cu nanocrystallite in silicon wafer, the implantation technique was used. The samples of silicon (100) wafers were implanted by $Cu^+$ ions at 100 keV and with varying the doses at room temperature. Post-annealing was performed at $800^{\circ}C$ with Ar environment. To investigate the formation of Cu nanocrystallite with ion doses and growth process by thermal annealing, SIMS and HRTEM(high resolution transmission electron microscopy)spectra were studied.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.23-29
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• 2006

Ultrasonic soldering of Si-wafer to FR-4 PCB at ambient temperature was investigated. The UBM of Si-substrate was Cu/ Ni/ Al from top to bottom with thickness of $0.4{\mu}m,\;0.4{\mu}m$, and $0.3{\mu}m$ respectively. The pad on FR-4 PCB comprised of Au/ Ni/ Cu from top to bottom with thickness of $0.05{\mu}m,\;5{\mu}m$, and $18{\mu}m$ respectively. Sn-3.5wt%Ag foil rolled to $100{\mu}m$ was used for solder. The ultrasonic soldering time was varied from 0.5 s to 3.0 s and the ultrasonic power was 1,400 W. The experimental results show that a reliable bond by ultrasonic soldering at ambient temperature was obtained. The shear strength increased with soldering time up to a maximum of 65 N at 2.5 s. The strength decreased to 34 N at 3.0 s because cracks were generated along the intermetallic compound between Si-wafer and Sn-3.5wt%Ag solder. The Intermetallic compound produced by ultrasonic soldering between the Si-wafer and the solder was $(Cu,Ni)_{6}Sn_{5}$.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.603-604
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• 2009

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.05a
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• pp.16.1-16.1
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• 2007

• Journal of Welding and Joining
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• v.32 no.3
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.