• Journal of Surface Science and Engineering
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• v.47 no.2
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• pp.68-74
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• 2014

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/$SiO_2$/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.

• Journal of Welding and Joining
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• v.20 no.2
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• pp.77-81
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• 2002

Many kinds of Pb-free solder have been investigated because of the environmental concerns. Sn-Ag-Cu system is well blown as most competitive Pb-free solder. However, since Sn-Ag-Cu system has relatively high melting point compared to Sn-Pb eutectic, it may a limitation, the some application. In this study, Bi and In contained solder of $Sn_3Ag_8Bi_5In$ which has relatively lower melting point, $188~204^{\circ}C$, was investigated. $Sn_3Ag_8Bi_5In$ solder ball of $500\mu\textrm{m}$ diameter was set on the Ni/Cu/Cr-UBM and reflow soldered in the range of $220~240^{\circ}C$ for 5~15s. The maximum shear strength of the solder ball was around 170mN by reflowing at $240^{\circ}C$ for 10s. Intermetallic compound formed on the UBM of Si-wafer was analysed by SEM(scanning electron microscope) and XRD(X-ray diffractometer).

• Journal of the Korean Ceramic Society
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• v.31 no.2
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• pp.227-233
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• 1994

The Bi-Sr-Ca-Cu-O thin films were deposited by RF-magnetron sputtering method on Si(P-111) wafer without a buffer layer and annealed at various temperatures in oxygen atmosphere. The temperature dependence of electrical resistance, the microstructure of intermediate phase, and the surface morphology of films were examined by four probe method, XRD, and SEM, respectively. The chemical composition and the depth profile of the films were determined by ESCA spectra. Thin films annealed at $600^{\circ}C$ and $700^{\circ}C$ in oxygen atmosphere showed onset temperatures of 90 K and 85K, and Tc(zero) of 22K and 31K, respectively. The sample annealed at $700^{\circ}C$ had the highest volume fraction of superconducting phase and showed smooth microsturcture. In ESCA spectra, the thin films were homogeneous with depth.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.446-450
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• 2001

In this study, microstructural and electrical properties of (Pb)(La,Nd)$TiO_3$ cerramics were investigated as a function of CuO addition. Taking into consideration Tc of $325^{\circ}C$, dynamic range of 49dB( at the wafer form) and density of $7.71g/cm^{3}$, it can be concluded that the specimen S2 sintered at $1200^{\circ}C$ is the best for the resonator application, Dynamic characteristics of energy-trapped 20MHz SMD type resonator as a function of internal dot size variation were also investigated. Dynamic range characteristics showed the highest value of 60.72dB at S2-4(dot size 1.13mm).

• Journal of Surface Science and Engineering
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• v.35 no.1
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• pp.11-16
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• 2002

As environmental concerns increasing, the electronics industry is focusing more attention on lead free solder alternatives. In this research, we have researched wettability of intermediate solder of Sn3Ag9Bi5In, which include In and Bi and has similar melting temperature to Sn37Pb eutectic solder. We investigated the wetting property of Sn3Ag9Bi5In. To estimate wettability of Sn3Ag9Bi5In solder on various substrates, the wettability of Sn3Ag9Bi5In solder on high-pure Cu-coupon was measured. Cu-coupon that plated Sn, Ni and Au/Ni and Si-wafer adsorbed Ni/Cu under bump metallurgy on one side. As a result, the wetting property of Sn3Ag9Bi5In solder is a little better than that of Sn37Pb and Sn3.5Ag.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.55-59
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• 2020

Copper Oxide (CuO) films were deposited on the n-type silicon wafer by rf magnetron sputtering for heterojunction solar cells. And then the samples were treated as a function of the annealing temperature (300-600℃) in a vacuum. Their electrical, optical and structural properties of the fabricated heterojunction solar cells were then investigated and the power conversion efficiencies (PCE) of the fabricated p-type copper oxide/n-type Si heterojunction cells were measured using solar simulator. After being treated at temperature of 500℃, the solar cells with CuO film have PCE of 0.43%, Current density of 5.37mA/㎠, Fill Factor of 39.82%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.446-450
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• 2001

In this study, microstructural and electrical properties of (Pb)(La,Nd)TiO$_3$ ceramics were investigated as a function of CuO addition. Taking into consideration Tc of 3$25^{\circ}C$, dynamic range of 49dB( at the wafer form) and density of 7.71g/㎤, it can be concluded that the specimen S2 sintered at 120$0^{\circ}C$ is the best for the resonator application. Dynamic characteristics of energy-trapped 20MHz SMD type resonator as a function of internal dot size variation were also investigated. Dynamic range characteristics showed the highest value of 60.72dB at S2-4(dot size 1.13mm).

• Korean Chemical Engineering Research
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• v.52 no.1
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• pp.26-39
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• 2014

Cu interconnection in electronic devices is fabricated via damascene process including Cu electrodeposition. In this review, Cu electrodeposition and superfilling for fabricating Cu interconnection are introduced. Superfilling results from the influences of organic additives in the electrolyte for Cu electrodeposition, and this is enabled by the local enhancement of Cu electrodeposition at the bottom of filling feature formed on the wafer through manipulating the surface coverage of organic additives. The dimension of metal interconnection has been constantly reduced to increase the integrity of electronic devices, and the width of interconnection reaches the range of few tens of nanometer. This size reduction raises the issues, which are the deterioration of electrical property and the reliability of Cu interconnection, and the difficulty of Cu superfilling. The various researches on the development of organic additives for the modification of Cu microstructure, the application of pulse and pulse-reverse electrodeposition, Cu-based alloy superfilling for improvement of reliability, and the enhancement of superfilling phenomenon to overcome the current problems are addressed in this review.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1401-1406
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• 2014

Knowledge of the manufacturing process of semiconductor devices in order to obtain a copper pattern using chemical mechanical polishing (CMP) planarization using a Wafer polishing process is applied with a thickness of the copper measured in real time, which need to be precisely controlled by, where the acquisition the actual thickness of the sensor value with the calculated value in terms of error can occur in the process. Approximated the actual measurement values so as to obtain a method using a simple average, moving average, compared to the results using filters onggo Strom real-time measurements of the thickness of the units of the control system to reduce the variation in the implementation of the method described for the.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.227-229
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• 2006

3차원 실장을 하기 위해서 딥핑 방법으로 전기적 신호를 전달할 수 있는 비아를 가진 실리콘 웨이퍼를 제작하였다. 레이저를 이용하여 실리콘 웨이퍼에 개구부가 원형에 가까운 관통 홀을 형성하였다. 관통 홀의 벽에 도금 방법으로 시드 층을 형성하였다. 관통 홀의 충전 금속은 Sn-3.5Ag-0.7Cu 솔더를 사용하였다. 딥핑 방법으로 시드 층과 솔더 사이의 확산 현상 이용하여 전기적 신호를 전달 할 수 있는 비아를 형성하였다. 비아 내부에 일부 기공과 크랙이 발견되기도 했으나 딥핑 방법을 통해서 빠른 시간 내에 비아를 가진 실리콘 웨이퍼를 제작 할 수 있었다.