• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.23-29
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• 2006

Ultrasonic soldering of Si-wafer to FR-4 PCB at ambient temperature was investigated. The UBM of Si-substrate was Cu/ Ni/ Al from top to bottom with thickness of $0.4{\mu}m,\;0.4{\mu}m$, and $0.3{\mu}m$ respectively. The pad on FR-4 PCB comprised of Au/ Ni/ Cu from top to bottom with thickness of $0.05{\mu}m,\;5{\mu}m$, and $18{\mu}m$ respectively. Sn-3.5wt%Ag foil rolled to $100{\mu}m$ was used for solder. The ultrasonic soldering time was varied from 0.5 s to 3.0 s and the ultrasonic power was 1,400 W. The experimental results show that a reliable bond by ultrasonic soldering at ambient temperature was obtained. The shear strength increased with soldering time up to a maximum of 65 N at 2.5 s. The strength decreased to 34 N at 3.0 s because cracks were generated along the intermetallic compound between Si-wafer and Sn-3.5wt%Ag solder. The Intermetallic compound produced by ultrasonic soldering between the Si-wafer and the solder was $(Cu,Ni)_{6}Sn_{5}$.

• Corrosion Science and Technology
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• v.9 no.6
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• Electronic Materials Letters
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• v.14 no.6
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• pp.718-724
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• 2018

With the development of photovoltaic industry, the cost of photovoltaic power generation has become the significant issue. And the metallization process has decided the cost of original materials and photovoltaic efficiency of the solar cells. Nowadays, double printing process has been introduced instead of one-step printing process for front contact of polycrystalline silicon solar cells, which can effectively improve the photovoltaic conversion efficiency of silicon solar cells. Here, the relative cheap Cu paste has replaced the expensive Ag paste to form Ag/Cu composite front contact of silicon solar cells. The photovoltaic performance and the cost of photovoltaic power generation have been investigated. With the optimization on structure and height of Cu finger layer for Ag/Cu composite double-printed front contact, the silicon solar cells have exhibited a photovoltaic conversion efficiency of 18.41%, which has reduced 3.42 cent per Watt for the cost of photovoltaic power generation.

• Tribology and Lubricants
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• v.28 no.4
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• pp.173-177
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• 2012

We used contact resonance force microscopy (CRFM) technique to determine the quantitative elastic properties of multiple materials integrated on the sub micrometer scale. The CRFM approach measures the frequencies of an AFM cantilever's first two flexural resonances while in contact with a material. The plain strain modulus of an unknown or test material can be obtained by comparing the resonant spectrum of the test material to that of a reference material. In this study we examined the following bumping materials for flip chip by using copper electrode as a reference material: NiP, Solder (Sn-Au-Cu alloy) and under filled epoxy. Data were analyzed by conventional beam dynamics and contact dynamics. The results showed a good agreement (~15% difference) with corresponding values determined by nanoindentaion. These results provide insight into the use of CRFM methods to attain reliable and accurate measurements of elastic properties of materials on the nanoscale.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.243.2-243.2
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• 2016

Tungsten (W) is recently gaining attention as a potential candidate to replace Cu in semiconductor metallization due to its expected improvement in material reliability and reduced resistivity size effect. In this study, the impact of electron scattering at grain boundaries in a polycrystalline W thin film was investigated. Two nominally 300 nm-thick films, a (110)-oriented single crystal film and a (110)-textured polycrystalline W film, were prepared onto (11-20) Al2O3 substrate and thermally oxidized Si substrate, respectively in identical fabrication conditions. The lateral grain size for the polycrystalline film was determined to be $119{\pm}7nm$ by TEM-based orientation mapping technique. The film thickness was chosen to significantly exceed the electron mean free path in W (16.1 and 77.7 nm at 293 and 4.2 K, respectively), which allows the impact of surface scattering on film resistivity to be negligible. Then, the difference in the resistivity of the two films can be attributed to grain boundary scattering. quantitative analyses were performed by employing the Mayadas-Shatzkes (MS) model, where the grain boundary reflection coefficient was determined to be $0.42{\pm}0.02$ and $0.40{\pm}0.02$ at 293 K and 4.2 K, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.1
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• pp.24-29
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• 2005

Chemical mechanical polishing (CMP) has been widely accepted for the global planarization of multi-layer structures in semiconductor manufacturing. Copper has been the candidate metallization material for ultra-large scale integrated circuits (ULSIs), owing to its excellent electro-migration resistance and low electrical resistance. However, it still has various problems in copper CMP process. Thus, it is important to understand the effect of the process variables such as turntable speed, head speed, down force and back pressure are very important parameters that must be carefully formulated in order to achieve desired the removal rates and non-uniformity. Using a design of experiment (DOE) approach, this study was performed investigating the main effect of the variables and the interaction between the various parameters during CMP. A better understanding of the interaction behavior between the various parameters and the effect on removal rate, non-uniformity and ETC (edge to center) is achieved by using the statistical analysis techniques. In the experimental tests, the optimum parameters which were derived from the statistical analysis could be found for higher removal rate and lower non-uniformity through the above DOE results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.174-175
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• 2007

A programmable metallization cell (PMC) memory structure with copper-saturated GeTe solid electrolyte films doped by nitrogen was prepared on a TiW bottom electrode by a co-sputtering technique at room temperature. The $Ge_{45}Te_{55}$ solid electrolyte films deposited with various $N_2$/Ar flow ratios showed an increase of crystallization temperature and especially, the electrolyte films deposited at $N_2$/Ar ratios above 30% showed a crystallization temperature above $400^{\circ}C$, resulting in surviving in a back-end process in semiconductor memory devices. The device with a 200 nm thick $Cu_{1-x}(Ge_{45}Te_{55})_x$ electrolyte switches at 1 V from an "off " state resistance, $R_{off}$, close to $10^5$ to an "on" resistance state, Ron, more than 20rders of magnitude lower for this programming current.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.53-59
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• 2001

Surfaces of PTFE and PVDF were modified by ion-assisted reaction (IAR) in which 1 keV $Ar^{+}$ ions were irradiated on the surface of the polymer with varying ion dose in an oxygen gas environment, and Cu, Pt, Al and Ag thin films were deposited on the modified polymers. Wettability of the modified polymers was largely improved by the formation of hydrophilic groups due to chemical reaction between polymer surface and the oxygen gas during IAR. The change in wettability in the modified polymers was also related to the change in surface morphology and roughness. Adhesion between metal films and polymers modified by IAR was significantly improved, so that no detachment was possible in the $Scotch^{TM}$ tape test. The increase of adhesion strength between the metal film and the modified PVDF was mainly attributed to the formation of hydrophilic groups, which interacted with the metal film. In the case of the modified PTFE, the enhanced adhesion to metal film could be explained by the change in surface morphology together with the formation of hydrophilic groups. The electrical properties of the metal films on the modified polymers were also investigated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.160-160
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• 2010

In this work, we investigate ohmic contacts to p-type GaN using a Pt/Cu/Au metallization scheme in order to achieve low resistance and thermally stable ohmic contact on p-GaN. An ohmic contact formed by a metal electrode deposited on a highly doped InGaN/GaN superlattice sturucture on p-GaN layer. The specific contact resistance is $1.56{\times}10^{-6}{\Omega}cm^2$ for the as-deposited sample, $1.35{\times}10^{-4}{\Omega}cm^2$ for the sample annealed at $250^{\circ}C$ and $6.88{\times}10^{-3}{\Omega}cm^2$ for the sample annealed at $300^{\circ}C$.