• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.05a
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• pp.148-149
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• 2015

본 연구에서는 전기 도금법을 이용하여 수 마이크로미터(${\mu}m$)에서 수십 마이크로미터 크기의 수지상(dendrite) 구리분말을 제조하였다. 구리 도금욕의 종류($Cu_2P_2O_7$, $CuSO_4$, $CuCl_2$), 인가 전위(E, Volt) 및 기판에 따른 수지상(Dendrite)의 형상적인 특성이 비교되었으며, 형상에 따른 겉보기밀도와 비표면적 측정(BET)이 진행되었다. 수지상의 2차 가지길이와 주축길이의 비(ratio)를 형상의 차이로 분류한 결과 염화구리 도금욕에서 0.14 로서 가장 큰 값을 가지며 겉보기 밀도는 $1.04g/cm^3$로 가장 낮은 값을 보였다.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Journal of the Korean institute of surface engineering
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• v.53 no.4
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• pp.190-199
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• 2020

Copper pyrophosphate baths were employed in order to study the dependencies of current efficiency, residual stress, surface morphology and microstructure of electrodeposited Cu thin layers on applied current density. The current efficiency was obtained to be more than about 90 %, independent of the applied current density. Residual stress of Cu electrodeposits was measured to be in the range of -30 MPa and 25 MPa with the increase of applied current density from 0.5 to 15 mA/㎠. Relatively smooth surface morphologies of the electodeposited Cu layers were obtained at an intermediate current range between 3 and 4 mA/㎠. The Cu electrodeposits showed FCC(111), FCC(200), and FCC(220) peaks and any preferred orientation was not observed in this study. The average crystalline size of Cu thin layers was measured to be in the range of 44~69 nm.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.3
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• pp.45-50
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• 1999

Copper has been widely used for the electronic parts, and especially spot welded one for the leads of condenser or resistor. However, copper is generally hard to be spot welded because of its low electrical resistivity. For this experiment, Sn-37%Pb solder which has relatively higher resistivity was coated on the Cu-sheet to improve the spot weldability of copper. As the experimental variables welding pressure was varied from 100 to 200kgf, welding time from 20 to 50ms, and welding current from 100 to 2500A. Experimental results showed that the solder coated Cu-sheet can be spot welded under the conditions of 400~2200A welding current, 100~200kgf pressure and 20-50ms welding time. The tensile shear strength of the spot welded joint increased with welding current up to the critical current, and after the critical value decreased with current.

• Korean Chemical Engineering Research
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• v.52 no.1
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• pp.26-39
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• 2014

Cu interconnection in electronic devices is fabricated via damascene process including Cu electrodeposition. In this review, Cu electrodeposition and superfilling for fabricating Cu interconnection are introduced. Superfilling results from the influences of organic additives in the electrolyte for Cu electrodeposition, and this is enabled by the local enhancement of Cu electrodeposition at the bottom of filling feature formed on the wafer through manipulating the surface coverage of organic additives. The dimension of metal interconnection has been constantly reduced to increase the integrity of electronic devices, and the width of interconnection reaches the range of few tens of nanometer. This size reduction raises the issues, which are the deterioration of electrical property and the reliability of Cu interconnection, and the difficulty of Cu superfilling. The various researches on the development of organic additives for the modification of Cu microstructure, the application of pulse and pulse-reverse electrodeposition, Cu-based alloy superfilling for improvement of reliability, and the enhancement of superfilling phenomenon to overcome the current problems are addressed in this review.

• Journal of the Korean Electrochemical Society
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• v.18 no.1
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• pp.7-16
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• 2015

Effects of chemical composition ($Cu^{2+}$, $K_4P_2O_7$ and additive concentrations) of baths on properties of Cu thin films electrodeposited from pyrophosphate copper bath were investigated. Current efficiency was increased to be near 100% with increasing $Cu^{2+}$ concentrations from 0.02 to 0.3M. Decrease of current efficiency was observed in the range of 1.5~1.8M $K_4P_2O_7$ concentration, but current efficiency of about 100% was measured in the ranges of both 0.9~1.3M and 2.1~2.4M. The change of additive concentration did not influenced current efficiency. Residual stress of electrodeposited Cu thin films was measured to be about 20 MPa below 0.15 M $Cu^{2+}$ concentration and increased with the increase of it to 0.25 M. Maximum residual stress of 120MPa was observed at 0.25M $Cu^{2+}$ concentration. On the other hand, residual stress decreased from 80 to near 0 MPa as $K_4P_2O_7$ concentration varied from 0.9 to 2.4M and but The change of additive concentration did not affected on residual stress. $Cu^{2+}$ and $K_4P_2O_7$ concentrations significantly affect on surface morphology of electrodeposited Cu thin films, but additive concentration slightly affected. From XRD analysis, the microstructures of electrodeposited Cu thin film was affected from the changes of $Cu^{2+}$ and $K_4P_2O_7$ concentrations, but not from that of additive concentration. Strong preferred orientation of (111) peak was observed with increasing $Cu^{2+}$ and $K_4P_2O_7$ concentrations.

• 한국전기화학회:학술대회논문집
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• 2000.10a
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• pp.18-18
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• 2000

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.472.2-472.2
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• 2014

현재 결정질 실리콘 태양전지의 전 후면 전극의 형성은 스크린 프린팅 방법이 주를 이루고 있다. 스크린 프린팅 방법은 쉽고 빠르게 인쇄가 가능한 반면 단가가 높고 금속 페이스트에 첨가된 여러 혼합물에 의해서 전극과 기판 사이의 저항이 크다는 단점이 있다. 본 논문에서는 도금을 이용하여 태양전지의 전극을 형성한 후 태양전지의 전기적 특성을 비교하였다. 또한 단일반사방지막($SiN_x$) 증착 후 도금을 이용한 전극 형성 시 반사방지막의 pin-hole에 의해 전극 이외의 표면에 도금이 되는 ghost plating 현상이 발생하게 되는데, 이를 방지하기 위해 thermal oxidation을 이용하여 SiO2/SiNx 이중반사 방지막을 증착함으로써 ghost plating을 최소화 시켰다. Ni을 이용하여 전극과 기판 사이의 저항을 낮추었으며, 주요 전극은 Cu 도금을 사용함으로써 단가를 낮추었으며 마지막으로 Cu전극의 산화를 방지하기 위해 Ag을 이용하여 얇게 도금하였다. 실험에 사용된 Si 웨이퍼 특성은 p-형, $156{\times}156mm2$, $200{\mu}m$, $0.5{\sim}3.0{\Omega}{\cdot}cm$ 이다. 웨이퍼는 표면조직화, p-n접합 형성, 반사방지막 코팅을 하였으며 스크린 프린팅 방법을 이용해 후면 전극을 인쇄하고 열처리 과정을 통해 전극을 형성하였다. 이 후 전면에 레이저를 이용해 전극 패턴을 형성한 후 도금을 실행하여 태양전지를 완성하였다. 완성된 태양전지는 솔라 시뮬레이터, QE 및 TLM패턴을 이용하여 전기적 특성을 분석하였으며, SEM과 linescan, 광학현미경 등을 이용하여 전극을 분석하였다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.104.1-104.1
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• 2018

열전소자는 열전현상을 이용한 재료로서 여기서 열전현상이란 열을 전기로 또는 전기를 열로 바꿀 수 있는 에너지 변환 현상을 의미한다. 그 중 Bi-Te계 열전소자는 $200^{\circ}C$이하의 온도에서 열전 효율이 우수하기 때문에 항공, 컴퓨터 등의 열전발전 또는 열전냉각 모듈에 널리 사용된다. 열전 모듈 제작시 Bi-Te 소자는 구리 기판에 접합하여 사용하게 되는데 이 때 솔더의 성분인 Sn과 기판의 Cu는 소자내로 확산하여 금속간 화합물을 형성한다. 이렇게 형성된 금속간 화합물은 접합강도를 저하시키는 원인뿐만 아니라 열전 성능을 저하시키는 원인이 된다. 본 연구에서는 이러한 접합강도와 열전성능의 저하를 막기 위해 BiTe 소자의 표면에 $4{\mu}m$두께의 Ni-P 도금 공정을 추가하여 Ni-P 도금층이 Cu와 Sn의 확산을 막는 방지층 역할을 하게 한다. 그리고 도금한 소자를 $3mm{\times}3mm{\times}3mm$로 커팅하여 구리 기판에 접합하여 열전 모듈을 제작하였다. 제작된 열전모듈의 단면을 EPMA분석한 결과 Ni-P 도금층이 확산방지층으로 잘 작용되었음을 확인하였다. 또한 접합강도 측정결과 도금을 하지 않은 Bi-Te소자에 비해 접합강도가 향상되었음을 확인하였다. 따라서 Ni-P도금을 실시함으로서 금속간 화합물 형성을 억제하고 열전모듈의 성능과 접합강도를 향상시킬 수 있었다.