• The KIPS Transactions:PartC
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• v.15C no.2
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• pp.133-140
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• 2008

In this paper, we propose a high performance elliptic curve cryptographic processor over $GF(2^{163})$. The proposed architecture is based on a modified Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for $GF(2^{163})$ field arithmetic. To achieve a high throughput rates, we design two new word-level arithmetic units over $GF(2^{163})$ and derive a parallelized elliptic curve point doubling and point addition algorithm with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with 2 times increased hardware complexity compared with the previous hardware implementation proposed by Shu. et. al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.12
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• pp.1863-1871
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• 2022

In the era of Fourth Industrial Revolution, secure networking technology is playing an essential role in the defense weapon systems. Encryption technology is used for information security. The safety of cryptographic technology, according to Kerchoff's principles, is based on secure key management of cryptographic technology, not on cryptographic algorithms. However, traditional centralized key management is one of the problematic issues in battlefield environments since the frequent movement of the forces and the time-varying quality of tactical networks. Alternatively, the system resources of each node used in the IoBT(Internet of Battlefield Things) environment are limited in size, capacity, and performance, so a lightweight key management system with less computation and complexity is needed than a conventional key management algorithm. This paper proposes a novel key escrow scheme in a lightweight manner for the IoBT environment. The safety and performance of the proposed technique are verified through numerical analysis and simulations.

• Journal of the Korea Society for Simulation
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• v.9 no.2
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• pp.15-25
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• 2000

Since data security problems are very important in the information age, cryptographic algorithms for encryption and decryption have been studied for a long time. The GOST(Gosudarstvennyi Standard or Government Standard) algorithm as a data encryption algorithm with a 256-bit key is a 64-bit block algorithm developed in the former Soviet Union. In this paper, we describe how to design an encryption chip based on the GOST algorithm. In addition, the GOST algorithm is compared with the DES(Data Encryption Standard) algorithm, which has been used as a conventional data encryption algorithm, in modeling techniques and their performance. The GOST algorithm whose key size is relatively longer than that of the DES algorithm has been expanded to get better performance, modeled in VHDL, and simulated for implementation with an CPLD chip.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.700-702
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• 1999

The protection of data which we want to keep secret from invalid users has become a main topic nowadays. This paper introduces a encryption scheme for protecting speech signals from eavesdropping. The proposed encryption scheme adopts a secure voice cryptographic algorithm based on the scrambling in frequency band. In order to improve the conventional speech signal encryption scheme, we have randomly permuted DCT coefficients of speech signal. Simulation results are included to show the performance of the proposed algorithm for secure transmission of speech signals.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.323-330
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• 2021

Recently, the advantages of high-speed arithmetic in quantum computers have been known, and interest in quantum circuits utilizing qubits has increased. The Grover algorithm is a quantum algorithm that can reduce n-bit security level symmetric key cryptography and hash functions to n/2-bit security level. Since the Grover algorithm work on quantum computers, the symmetric cryptographic technique and hash function to be applied must be implemented in a quantum circuit. This is the motivation for these studies, and recently, research on implementing symmetric cryptographic technique and hash functions in quantum circuits has been actively conducted. However, at present, in a situation where the number of qubits is limited, we are interested in implementing with the minimum number of qubits and aim for efficient implementation. In this paper, the domestic hash function LSH is efficiently implemented using qubits recycling and pre-computation. Also, major operations such as Mix and Final were efficiently implemented as quantum circuits using ProjectQ, a quantum programming tool provided by IBM, and the quantum resources required for this were evaluated.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.3
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• pp.113-123
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• 2007

This paper presents a high-performance elliptic curve cryptographic processor over $GF(2^m)$. The proposed design adopts Lopez-Dahab Montgomery algorithm for elliptic curve point multiplication and uses Gaussian normal basis for $GF(2^m)$ field arithmetic operations. We select m=163 which is the smallest value among five recommended $GF(2^m)$ field sizes by NIST and it is Gaussian normal basis of type 4. The proposed elliptic curve cryptographic processor consists of host interface, data memory, instruction memory, and control. We implement the proposed design using Xilinx XCV2000E FPGA device. Based on the FPGA implementation results, we can see that our design is 2.6 times faster and requires significantly less hardware resources compared with the previously proposed best hardware implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.37-47
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• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.4
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• pp.91-103
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• 2009

A cryptographic module (CM) is an implementation of various cryptographic algorithms and functions by means of hardware or software, When a CM is validated or certified under the CM validation program(CMVP), a finite state model(FSM) of the CM should be developed and provided, However, guides or methods of modeling and analysis of a FSM is not well-known, because the guide is occasionally regarded as a proprietary know-how by developers as well as verifiers of the CM. In this paper, we propose a set of guides on modeling and analysis of a FSM, which is needed for validation of a CM under CMVP, and a transition test path generation algorithm, as well as implement a simple modeling tool (CM-Statecharter). A FSM of a CM is modeled by using the Statechart of UML 2.0, Statechart, overcoming weakness of a FSM, is a formal and easy specification model for finite state modeling of a CM.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2754-2759
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• 2011

With information communications and RFID/USN environments merged wire/wireless networks are generalized. In this viewpoint, WAP is used by communication protocol for the data communication in the field of wireless environment. WTLS developed for the secure communications optimize TLS adapted wireless environment in the TCP/IP internet protocol. But WTLS denote WAP security problem, end-to-end problem, and power consumption, etc. Therefore in this paper we proposed WTLS cryptographic algorithm eliminated WTLS disadvantages. Proposed algorithm solved power consumption, calculated complexity, and security problems because it is not unique but hybrid form.