• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.584-586
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• 2017

In this paper we provide a unified crypto core that integrates lightweight symmetric cryptography and authentication. The crypto core implements a unified 128 bit key architecture of PRESENT encryption algorithm and a new lightweight encryption algorithm. The crypto core also consist of an authentication unit which neglects the use of hashing algorithms. Four algorithms are used for authentication which come from the Hopper-Blum (HB) and Hopper-Blum-Munilla-Penado (HB-MP) family of lightweight authentication algorithms: HB, HB+, HB-MP and HB-MP+. A unified architecture of these algorithms is implemented in this paper. The unified cryptosystem is designed using Verilog HDL, simulated with Modelsim SE and synthesized with Xilinx Design Suite 14.3. The crypto core synthesized to 1130 slices at 189Mhz frequency on Spartan6 FPGA device.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.64-70
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• 2010

In this paper, we study and develope a special secure Dongle to be adapted in GSM SmartPhone for secure voice communication to the serial 20-pin connector in SmartPhone. We design and implement the Dongle module hardware, firmware, and software including cipher crypto-synchronization and cipher algorithm. Also we study and emulate the SmartPhone GUI software interface including communication software module to the Dongle. Finally, we analyze the performances of crypto-synchronization in some noisy environment and also we test the secure Dongle module.

• Proceedings of the Korea Multimedia Society Conference
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• 2001.11a
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• pp.617-622
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• 2001

컴퓨터 및 네트워크의 급속한 성장은 정보 사회로의 발전을 이행해 왔으며, 수많은 정보들이 네트워크를 통해 공유 및 교환되고 있다. 이들은 공개된 네트워크를 전재로 수행되므로, 다양한 형태의 공격으로부터 노출되어 있다. 이를 공격에 대응하고 나아가 사용자 및 메시지 인증을 수행키 위해 각광을 받고 있는 방법 중에 하나로서 디지털 서명을 들 수 있다. 그러나 일반 디지털 서명 방식은 누구나 서명 확인이 가능하므로 서명자의 익명성과 비밀성을 보장해야 하는 전자 투표, 전자 회의 및 전자 입찰 등과 같은 응용 분야에 적용할 경우에는 문제점을 드러내고 있다. 따라서 이들 응용 분야들은 기본적으로 서명자의 신원을 보장하여야 하며, 필요할 경우 이를 확인할 수 있어야 한다. 현재 이와 관련하여 부인 방지 서명 방식과 이를 개선한 수신자 지정 서명 방식이 제안되어 있다. 그러나 이 방식들은 서명자의 익명성이 수신자에게 의존하기 때문에 수신자에 의해 신원이 노출될 수 있었다. 동시에 이들 방식은 메시지 부가형 서명에 기초하므로 전송되는 서명 정보상의 메시지가 제 3자에게 노출되는 결과를 초래한다. 본 고에서는 서명자의 익명성을 보장하면서, 오직 수신자만이 서명자의 신분을 확인할 수 있는 Crypto-Cert 디지털 서명 방식에 대해 고찰한다. 특히 본 방식에서는 필요할 경우 서명자의 신원을 확인할 수 있으며, 전송 메시지에 대해 기밀성을 확보하고 있으므로 다양한 응용 분야에 적용가능하다.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.121-127
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• 2012

An integrated crypto engine for encryption and decryption of AES algorithm based on unified data-path architecture is efficiently designed and implemented in this paper. In order to unify the design of encryption and decryption, internal steps in single round is adjusted so as to operate with columns after row operation is completed and efficient method for a buffer is developed to simplify the Shift Rows operation. Also, only one S-box is used for both key expansion and crypto operation and Key-Box saving expended key is introduced provide the key required in encryption and decryption. The functional simulation based on ModelSim simulator shows that 164 clocks are required to process the data of 128bits in the proposed engine. In addition, the proposed engine is implemented with 6,801 gates by using Xilinx Synthesizer. This demonstrate that 40% gates savings is achieved in the proposed engine, compared to individual designs of encryption and decryption engine.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.10a
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• pp.797-800
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• 2000

최근 정보 보안에 대한 연구 및 개발이 활발하게 이루어지고 있으며, 그 중 보안 API 는 보안 서비스를 제공하는 인터페이스 규격으로서 중요성이 증대되고 있다. 대표적인 보안 API 로는 MS의 CryptoAPI, Intel 보안 구조인 CDSA 의 CSSM API, IETF의 GSS-API/IDUP-GSS-API, X/Open 그룹의 GCS-API 등이 있다. 보안 API 는 응용 개발자와 보안 장비 개발자의 편리성 및 독립성을 최대한 보장할 수 있어야 하지만, 실제 구현 환경에서 부딪치는 문제는 OS 플랫폼이 기반이 되지 못한 경우 시스템 보안 구조의 계층화가 어렵고, 실제 구현 환경에서 호환성을 보장할 수 없다는 것이다. 이러한 관점에서 MS의 CryptoAPI는 응용 및 보안 장비의 개발 규격 및 절차를 제안하고 있으며, 두 분야의 개발자 사이의 연동은 시스템 OS인 Windows가 담당하고 있다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.6
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• pp.105-110
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• 2005

The linearized polynomial fan be regarded as a generalization of the identity function so that the inverse of the linearized polynomial is a generalization of e inverse function. Since the inverse function has so many good cryptographic properties, the inverse of the linearized polynomial is also a candidate of good Boolean functions. In particular, a construction method of vector resilient functions with high algebraic degree was proposed at Crypto 2001. But the analysis about the algebraic degree of the inverse of the linearized Polynomial. Hence we correct the inexact result and give the exact maximal algebraic degree.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.