• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.213-213
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• 2016

현재 반도체 산업에서는 디바이스의 고 집적화, 고 수율을 목적으로 패턴의 미세화 및 웨이퍼의 대면적화와 같은 이슈가 크게 부각되고 있다. 다중 패터닝(multiple patterning) 기술을 통하여 고 집적 패턴을 구현이 가능해졌으며, 이와 같은 상황에서 각 패턴의 임계치수(critical dimension) 변화는 패턴의 위치 및 품질에 큰 영향을 끼치기 때문에 포토마스크의 임계치수 균일도(critical dimension uniformity, CDU)가 제작 공정에서 주요 파라미터로 인식되고 있다. 반도체 광 리소그래피 공정에서 크롬(Cr) 박막은 사용되는 포토 마스크의 재료로 널리 사용되고 있으며, 이러한 포토마스크는 fused silica, chrome, PR의 박막 층으로 이루어져 있다. 포토마스크의 패턴은 플라즈마 식각 장비를 이용하여 형성하게 되므로, 식각 공정의 플라즈마 균일도를 계측하고 관리 하는 것은 공정 결과물 관리에 필수적이며 전체 반도체 공정 수율에도 큰 영향을 미친다. 흔히, 포토마스크 임계치수는 플라즈마 공정에서의 라디칼 농도 및 식각 선택비에 의해 크게 영향을 받는 것으로 알려져 왔다. 본 연구에서는 Cr 포토마스크 에칭 공정에서의 Cl2/O2 공정 플라즈마에 대해 O2 가스 주입량에 따른 식각 선택비(etch selectivity) 변화를 계측하여 선택비 제어를 통한 Cr 포토마스크 임계치수 균일도 향상을 실험적으로 입증하였다. 연구에서 사용한 플라즈마 계측 방법인 발광분광법(OES)과 optical actinometry의 적합성을 확인하기 위해서 Cl2 가스 주입량에 따른 actinometer 기체(Ar)에 대한 atomic Cl 농도비를 계측하였고, actinometry 이론에 근거하여 linear regression error 1.9%을 보였다. 다음으로, O2 가스 주입비에 따른 Cr 및 PR의 식각률(etch rate)을 계측함으로써 식각 선택비(etch selectivity)의 변화율이 적은 O2 가스 농도 범위(8-14%)를 확인하였고, 이 구간에서 임계치수 균일도가 가장 좋을 것으로 예상할 수 있었다. (그림 1) 또한, spatially resolvable optical emission spectrometer(SROES)를 사용하여 플라즈마 챔버 내부의 O atom 및 Cl radical의 공간 농도 분포를 확인하였다. 포토마스크의 임계치수 균일도(CDU)는 챔버 내부의 식각 선택비의 변화율에 강하게 영향을 받을 것으로 예상하였고, 이를 입증하기 위해 각각 다른 O2 농도 환경에서 포토마스크 임계치수 값을 확인하였다. (표1) O2 11%에서 측정된 임계치수 균일도는 1.3nm, 그 외의 O2 가스 주입량에 대해서는 임계치수 균일도 ~1.7nm의 범위를 보이며, 이는 25% 임계치수 균일도 향상을 의미함을 보인다.

• Korean Journal of Optics and Photonics
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• v.15 no.1
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• pp.79-85
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• 2004

We report on a transmittance controlled photomask with phase patterns on the back quartz surface. Theoretical analysis for changes in illumination pupil shape with respect to the variation of size and density of backside phase patterns and experimental results for improvement of critical dimension uniformity on a wafer by using the transmittance controlled photomask are presented. As phase patterns for controlling transmittance of the photomask we used etched contact-hole type patterns with 180" rotative phase with respect to the unetched region. It is shown that pattern size on the backside of the photomask must be made as small as possible in order to keep the illumination pupil shape as close as possible to the original pupil shape and to achieve as large an illumination intensity drop as possible at a same pattern density. The distribution of illumination intensity drop suitable for correcting critical dimension error was realized by controlling pattern density of the contact-hole type phase patterns. We applied this transmittance controlled photomask to a critical layer of DRAM (Dynamic Random Access Memory) having a 140nm design rule and could achieve improvement of the critical dimension uniformity value from 24.0 nm to 10.7 nm in 3$\sigma$.TEX>.

• Korean Journal of Optics and Photonics
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• v.18 no.1
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• pp.74-78
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• 2007

We report theoretical and experimental results for application of transmittance-controlled photomask technology to ArF lithography. The transmittance-controlled photomask technology is thought to be a promising technique fo critical dimension (CD) uniformity correction on a wafer by use of phase patterns on the backside of a photomask. We could theoretically reproduce experimental results for illumination intensity drop with respect to the variation of backside phase patterns by considering light propagation from the backside to the front side of a photomask at the ArF lithography wavelength. We applied the transmittance-controlled photomask technology to ArF lithography for a critical layer of DRAM (Dynamic Random Access Memory) having a 110-nm design rule and found that the in-field CD uniformity value was improved from 13.8 nm to 9.7 nm in $3{\sigma}$.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.1269-1270
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• 2013

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.1273-1274
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• 2013

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.400-400
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• 2009

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.46.5-46
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• 2002

As device dimension shrinks down to sub 100nm, it is increasingly important to monitor plasma states. Plasma etching is a key means to fine patterning of thin films. Many parameters are involved in etching and each parameter has different impact on process performances, including etch rate and profile. The uniformity of etch responses should be maintained high to improve device yield and throughput. The uniformity can be measured on any etch response. The most difficulty arises when attempting to characterize etched profile. Conventionally, the profile has been estimated by measuring the slope or angle of etched pattern. One critical drawback in this measurement is that this is unable to cap...

• Journal of Institute of Control, Robotics and Systems
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• v.4 no.4
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• pp.506-516
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• 1998

In this paper, an algorithm is proposed to detect the malfunction of plasma-etching characteristics using EPD signal trajectories. EPD signal trajectories offer many information on plasma-etching process state, so they must be considered as the most important data sets to predict the wafer states in plasma-etching process. A recent work has shown that EPD signal trajectories were successfully incorporated into process modeling through critical parameter extraction, but this method consumes much effort and time. So Principal component analysis(PCA) can be applied. PCA is the linear transformation algorithm which converts correlated high-dimensional data sets to uncorrelated low-dimensional data sets. Based on this reason neural network model can improve its performance and convergence speed when it uses the features which are extracted from raw EPD signals by PCA. Wafer-state variables, Critical Dimension(CD) and uniformity can be estimated by simulation using neural network model into which EPD signals are incorporated. After CD and uniformity values are predicted, proposed algorithm determines whether malfunction values are produced or not. If malfunction values arise, the etching process is stopped immediately. As a result, through simulation, we can keep the abnormal state of etching process from propagating into the next run. All the procedures of this algorithm can be performed on-line, i.e. wafer to wafer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.100-105
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• 2004

The influencing factors on the OPC (optical proximity correction) results are quantitatively analyzed using OPCed L/S patterns. ${\sigma}$ values of proximity variations are measured to be 9.3 nm and 15.2 nm for PR-A and PR-B, respectively. The effect of post exposure bake condition is assessed. 16.2 nm and 13.8 nm of variations are observed. Proximity variations of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate the OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4, 13.9, and 15.2 nm are observed for the mask mean-to-targets of 0, 2 and 4 nm, respectively. The decrease the OPC grid size from 1 nm to 0.5 nm enhances the correction resolution and the OCV is reduced from 14.6 nm to 11.4 nm. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The critical dimension (CD) uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 9.9 nm and 8.7 nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved. The decrease of OPC grid size is shown to improve not only the proximity correction, but also the uniformity.