• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1161-1164
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• 1998

We designed a DSP core simulator with C language, that is able to simulate 5-stage pipelined DSP core, named YS-DSP. It can emulate all 5 stage pipelines in the DSP core. It can also emulate memory access, exception processing, and DSP parallel processing. Each pipeline stage is implemented by combination of one or more functions to process parts of each stage. After modeling and validating the simulator, we can use it to verify and to complement the DSP core HDL model and to enhance its performance.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2005년도 춘계학술대회 논문집
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• pp.89-92
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• 2005

Each 3D visualization program has its own different structure as for the purpose. This paper describes the design and development of an on-line 3D core data visualization program, $RocDis^{TM}$, for the nuclear simulator. It is possible to analyze the inside of the core status including neutron flux, relative power, moderator and fuel temperature in 3D distribution. Some of other essential information, axial flux distribution etc. could also display in 2D graphs. This program would be design, tuning and training for the simulator core model.

• 한국통신학회논문지
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• 제36권1B호
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• pp.71-79
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• 2011

본 논문은 어플리케이션에 최적화된 임베디드 시스템 설계에 있어 효율적인 설계 공간을 탐색할 수 있도록 머신 기술 언어를 기반으로 한 컴파일드 코드 방식 시뮬레이터 생성 시스템을 제안한다. 제안된 시스템 event-driven 시뮬레이션의 융통성을 유지하면서 많은 시뮬레이션 시간을 소요하는 인스트럭션 펫치와 디코딩 과정을 정적으로 결정하여 빠른 수행시간을 갖는 컴파일드 코드 방식 시뮬레이터를 생성한다. 생성된 시뮬레이터는 임베디드 코어의 성능 측정을 위한 사이클 수준과 인스트럭션 수준의 시뮬레이션을 가진다. 구축된 컴파일드 코드 방식 시뮬레이터 생성기의 효율성을 확인하기 위해 JPEG 인코더 어플리케이션에 대한 아키텍처 탐색을 수행하였다. 제안된 시스템은 MIPS R3000 프로세서의 초기 임베디드 코어로 시작하여 어플리케이션에 최적화된 임베디드 코어를 얻어내었다. 이 과정에서 많은 시뮬레이션 시간이 요구되었다. 사이클 수준 컴파일드 코드 빙식 시뮬레이터는 event-driven 시뮬레이션의 정확성을 가지며 평균 21.7%의 향상된 시뮬레이션의 수행 속도를 보인다.

• 한국유체기계학회 논문집
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• 제15권4호
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• pp.5-11
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• 2012

To identify the flow characteristics of the SMART reactor, a flow distribution model test and a numerical simulation are performed in KAERI. Among several part of the SMART reactor, the fuel assemblies are simulated using simulators because of the complexity. The geometries of the core in the SMART reactor and simulator are different, but some similarities are maintained such as the ratio of pressure drop in the vertical and cross directions. There are cross flow holes in each core simulator to reproduce the cross flow of SMART fuel assemblies. To know the flow characteristics of the cross flow, numerical analysis is performed. As the cross flow area is decreased, the pressure drop between inlet and outlet is decreased. Also, when the flow imbalance between two core simulators is constant, the cross flow area does not significantly affect the cross flow.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2005년도 춘계학술대회 논문집
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• pp.129-133
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• 2005

This paper describes the methodology of connecting MASTER (Multi-purpose Analyzer for Static and Transient Effects of Reactors) to simulator system, system configuration, and previous test. The actual simulator environment for Youngkwang Unit1 has been developed. It is impossible for the simulator server to execute MASTER code by limitation of computer performance. So, environment of distributed system was developed, and it had a synchronization task. As MASTER and simulator module should be synchronized in different device, the connection of communication was tested and verified.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.117-120
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• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• 전자공학회논문지CI
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• 제40권5호
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• pp.298-305
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• 2003

본 논문은 디지털 회로의 검증 및 테스팅에 유용한 128 채널 하드웨어 시뮬레이터의 구현에 대하여 기술하였다. 하드웨어 시뮬레이터는 로직분석기와 신호발생기의 기능을 동시에 수행한다. 각 채널에 해당하는 코어 모듈은 독립적인 메모리와 내부 모드를 가지고서 하나의 컨트롤러처럼 동작하기 때문에 코어모듈을 추가함으로써 채널 수를 쉽게 확장할 수 있다. 또한 PC를 기반으로 하고 있어 저가형 시스템으로 구현 가능하고, 편리한 GUI(Graphic User Interface) 구성을 할 수 있다. FPGA를 이용하여 구현된 시뮬레이터는 최대 50MHz에서 동작하며 평균 55W의 전력을 소모한다.

• Nuclear Engineering and Technology
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• 제56권3호
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• pp.933-940
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• 2024

A macroscopic cross section generation model was developed for the conceptual horizontal, compact high temperature gas reactor (HC-HTGR). Because there are many sources of spectral effects in the design and analysis of the core, conventional LWR methods have limitations for accurate simulation of the HC-HTGR using a neutron diffusion core neutronics simulator. Several super-cell model configurations were investigated to consider the spectral effect of neighboring cells. A new history variable was introduced for the existing library format to more accurately account for the history effect from neighboring nodes and reactivity control drums. The macroscopic cross section library was validated through comparison with cross sections generated using full core Monte Carlo models and single cell cross section for both 3D core steady-state problems and 2D and 3D depletion problems. Core calculations were then performed with the AGREE HTR neutronics and thermal-fluid core simulator using super-cell cross sections. With the new history variable, the super-cell cross sections were in good agreement with the full core cross sections even for problems with significant spectrum change during fuel shuffling and depletion.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2001년도 춘계학술대회 논문집
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• pp.58-65
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• 2001

Many changes in the railway environment has directly affected to the railway company. To cope immediately with the influence of environment and to promote productivity, the railway company has to introduce an efficient train operation system and related core technologies. The railway system is composed or large-scale infrastructures ann high-cost trains. Simulation method is one or core technologies and also is efficient tool for planning and analyzing this kind of complex system. The purpose of this research is to develop multi-train traffic simulator considering high-speed train for GyongBu-Line. To achieve this objective, the elements of railway system was analyzed, and as a result, a data structure modeling for the railway system such as rail-Tine infrastructure, rain, timetable and operational route is presented. The developed simulator is composed of three major part : input-module, main-module, and output module. The concept and brief explanation of each module will be treated.

• 한국철도학회논문집
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• 제4권2호
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• pp.47-54
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• 2001

Railway companies have been faced with many changes in the railway environment. To cope immediately with the influence of environment and to improve productivity, an efficient train operation system and related core technologies must be introduced. The railway system is composed of large scale infrastructures and high-cost trains. Simulation method is one of core technologies and also efficient tool for planning and analyzing these kinds of complex system. In this research, we review basic simulation programming models and present a modeling for the elements of railway system such as rail-line infrastructure, train, time table and operational route. Additionally, some considerations on the development of multi-train traffic simulator for KyongBu-line are discussed.