• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1161-1164
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• 1998

We designed a DSP core simulator with C language, that is able to simulate 5-stage pipelined DSP core, named YS-DSP. It can emulate all 5 stage pipelines in the DSP core. It can also emulate memory access, exception processing, and DSP parallel processing. Each pipeline stage is implemented by combination of one or more functions to process parts of each stage. After modeling and validating the simulator, we can use it to verify and to complement the DSP core HDL model and to enhance its performance.

• Proceedings of the Korea Society for Simulation Conference
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• 2005.05a
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• pp.89-92
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• 2005

Each 3D visualization program has its own different structure as for the purpose. This paper describes the design and development of an on-line 3D core data visualization program, $RocDis^{TM}$, for the nuclear simulator. It is possible to analyze the inside of the core status including neutron flux, relative power, moderator and fuel temperature in 3D distribution. Some of other essential information, axial flux distribution etc. could also display in 2D graphs. This program would be design, tuning and training for the simulator core model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• The KSFM Journal of Fluid Machinery
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• v.15 no.4
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• pp.5-11
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• 2012

To identify the flow characteristics of the SMART reactor, a flow distribution model test and a numerical simulation are performed in KAERI. Among several part of the SMART reactor, the fuel assemblies are simulated using simulators because of the complexity. The geometries of the core in the SMART reactor and simulator are different, but some similarities are maintained such as the ratio of pressure drop in the vertical and cross directions. There are cross flow holes in each core simulator to reproduce the cross flow of SMART fuel assemblies. To know the flow characteristics of the cross flow, numerical analysis is performed. As the cross flow area is decreased, the pressure drop between inlet and outlet is decreased. Also, when the flow imbalance between two core simulators is constant, the cross flow area does not significantly affect the cross flow.

• Proceedings of the Korea Society for Simulation Conference
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• 2005.05a
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• pp.129-133
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• 2005

This paper describes the methodology of connecting MASTER (Multi-purpose Analyzer for Static and Transient Effects of Reactors) to simulator system, system configuration, and previous test. The actual simulator environment for Youngkwang Unit1 has been developed. It is impossible for the simulator server to execute MASTER code by limitation of computer performance. So, environment of distributed system was developed, and it had a synchronization task. As MASTER and simulator module should be synchronized in different device, the connection of communication was tested and verified.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.117-120
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• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.298-305
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• 2003

This paper describes a 128-channel hardware simulator that is useful for verification and testing of digital circuits. It performs logic analyzer function and signal generator function at the same time. The core module, which implements one channel of the simulator, operates as a controller with independent memory and internal mode. Therefore, we can easily extend the number of channels with addition of core module. Moreover, since the simulator was implemented as a PC based system, one can construct a low-cost system and can configure convenient GUI(Graphic User Interface) environment. The simulator implemented using FPGA operates at 50Mhz and consumes 55W power as average.

• Nuclear Engineering and Technology
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• v.56 no.3
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• pp.933-940
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• 2024

A macroscopic cross section generation model was developed for the conceptual horizontal, compact high temperature gas reactor (HC-HTGR). Because there are many sources of spectral effects in the design and analysis of the core, conventional LWR methods have limitations for accurate simulation of the HC-HTGR using a neutron diffusion core neutronics simulator. Several super-cell model configurations were investigated to consider the spectral effect of neighboring cells. A new history variable was introduced for the existing library format to more accurately account for the history effect from neighboring nodes and reactivity control drums. The macroscopic cross section library was validated through comparison with cross sections generated using full core Monte Carlo models and single cell cross section for both 3D core steady-state problems and 2D and 3D depletion problems. Core calculations were then performed with the AGREE HTR neutronics and thermal-fluid core simulator using super-cell cross sections. With the new history variable, the super-cell cross sections were in good agreement with the full core cross sections even for problems with significant spectrum change during fuel shuffling and depletion.

• Proceedings of the KSR Conference
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• 2001.05a
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• pp.58-65
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• 2001

Many changes in the railway environment has directly affected to the railway company. To cope immediately with the influence of environment and to promote productivity, the railway company has to introduce an efficient train operation system and related core technologies. The railway system is composed or large-scale infrastructures ann high-cost trains. Simulation method is one or core technologies and also is efficient tool for planning and analyzing this kind of complex system. The purpose of this research is to develop multi-train traffic simulator considering high-speed train for GyongBu-Line. To achieve this objective, the elements of railway system was analyzed, and as a result, a data structure modeling for the railway system such as rail-Tine infrastructure, rain, timetable and operational route is presented. The developed simulator is composed of three major part : input-module, main-module, and output module. The concept and brief explanation of each module will be treated.

• Journal of the Korean Society for Railway
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• v.4 no.2
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• pp.47-54
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• 2001

Railway companies have been faced with many changes in the railway environment. To cope immediately with the influence of environment and to improve productivity, an efficient train operation system and related core technologies must be introduced. The railway system is composed of large scale infrastructures and high-cost trains. Simulation method is one of core technologies and also efficient tool for planning and analyzing these kinds of complex system. In this research, we review basic simulation programming models and present a modeling for the elements of railway system such as rail-line infrastructure, train, time table and operational route. Additionally, some considerations on the development of multi-train traffic simulator for KyongBu-line are discussed.