• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.1110-1115
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• 1991

Tne mathematical modeling and analysis results of a dataflow logic solving processor(DFLSP) for programmable logic controller(PLC) are proposed in this paper. The logic program language is formalized using a dataflow graph model. From this dataflow graph, the instruction precedence relationship, and deadlock problems, which are major properties of a logic program, are described.

• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.948-950
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• 1997

This paper presents a basic interposing logic program to control nuclear power plant. In this paper we select a target control loop among the whole interposing modules, develop logic algorithm and functional software to compose target control loop. After that we carry out V&V(Verification and Validation) into the developed logic program to improve quality and reliability.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.2
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• pp.92-99
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• 2014

The paper is related to smart maximum power system based on program logic. Especially, this system compares the total demand power with the target power by using the signal from the digital kilo watt meter. Based on the power information by the maximum power control equipment the consumed future power is anticipated. In addition, through consumed future power the controllable target power is set, and it applies on the maximum power control equipment. User or manager would control the load efficiently through the simple programming which could control load based on the control sequence and relay. To begin with the conventional maximum power control algorithm is surveyed, and the smart maximum power control system based on program logic is used, and the new algorithm from full load to proportion shut down is proposed by using PLC program. the validity of the proposed control scheme is investigated by both simulation results.

• Journal of the Korea Society for Simulation
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• v.15 no.1
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• pp.11-17
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• 2006

This paper shows a case study of designing a PLC logic simulator that was developed to simulate and verify PLC control programs for nuclear plant systems. The nuclear control system requires strict restrictions rather than normal process control system does, as it works with a high-risky and dangerous nuclear plant. One is that it should assure the safeness of the control programs by exploiting severe testing. The other restriction is that the control programs should be executed fast enough such that they could control multi devices concurrently in real-time. To cope with these restrictions, we devised a logic compiler which generates C-code programs from given PLC logic programs. Once the logic program was translated into C-code, the program could be analyzed by conventional software analysis tools and could be used to construct a fast logic simulator after cross-compiling, in fact, that is a kind of compiled-code simulator.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.10
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• pp.5134-5139
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• 2013

Ladder Diagram(LD) or Sequential Function Chart(SFC) is used for the design of complex modern control system with Programmable logic controller(PLC). LD is the most widely utilized among PLC standard language. But recently, SFC is used frequently. SFC is very easy to grasp the sequential flow of control logic but is difficult for describing combinational logic. When the interrupt factor is occurred, the main program is stopped. And after the interrupt program is completed, the main program is restart. Therefore the more complex the interrupt program, the main program is interrupted downtime will be that much longer. In this paper, we propose the method for interrupt implementation without the dwell time of the main program by SFC language and confirm his feasibility through the simulation.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.8
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• pp.834-841
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• 2006

Recently, many enterprises are installing AMSs(Automated Manufacturing Systems) for their competitive advantages. As the level of automation increases, proper design and validation of control logic is a imperative task for the successful operation of AMSs. However, current discrete event simulation methods mainly focus on the performance evaluation. As a result, they lack the modeling capabilities for the detail logic of automated manufacturing system controller. Proposed in this paper is a method of validation of the controller logic for automated material handling system using an object-oriented design and simulation. Using this method, FA engineers can validate the controller logic easily in earlier stage of system design, so they can reduce the time for correcting the logic errors and enhance the productivity of control program development Generated simulation model can also be used as a communication tool among FA engineers who have different experiences and disciplines.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.8
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.634-638
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• 1990

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP (dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. The proposed DFLSP is adequate for high speed programmable logic controllers and gets rid of data synchronization problem in hardware level. The performance of the proposed DFLSP is analyzed using computer simulations and prototype hardware. With single processing element, the logic solving time is 144 usec per 1K steps of logic program and with eight processing elements, the logic solving time is 23 usec per 1K steps of logic program with reasonable assumptions.