• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.6
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• pp.299-305
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• 2020

We have developed a scheduler that additionally consider network performance by extending the Kubernetes developed to manage lots of containers in cloud computing nodes. The network delay adapt characteristics of the compute nodes were learned during server operation and the learned results were utilized to develop placement algorithm by considering the existing measurement units, CPU, memory, and volume together, and it was confirmed that the low delay network service was provided through placement algorithm.

• The Journal of the Convergence on Culture Technology
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• v.7 no.1
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• pp.615-619
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• 2021

This study focuses on memory systems that are optimized to increase performance and energy efficiency in many embedded systems such as IoT, cloud computing, and edge computing, and proposes a performance improvement technique. The proposed technique improves memory system performance based on machine learning algorithms that are widely used in many applications. The machine learning technique can be used for various applications through supervised learning, and can be applied to a data classification task used in improving memory system performance. Data classification based on highly accurate machine learning techniques enables data to be appropriately arranged according to data usage patterns, thereby improving overall system performance.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.5
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• pp.777-784
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• 2023

A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.12
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• pp.435-440
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• 1983

The methods of forming the bus impedance matrix, which is mainly employed in fault analysis of power system, can be generally classified in catagories, (1) the one being the inverse matrix of bus admittance matrix, and (2) the other the bus impedance matrix succesive formation method by particular algorithms. The former method is theouetically elegant, but the formation and inverse of complex bus admittance matrix for large power system requires too much amounts of computer memory space and computing time. The latter method also requires too much memory space. Therefore, in this paper, an algorithm and computer program is introduced for the formation of a sparse bus impedance matrix which generates only the matching terms of the admittance matrix. So, this method can reduce the computer memory and computing time, and can be applied to fault analysis of large power system by small digital computer.

• Journal of the Korean Data and Information Science Society
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• v.26 no.5
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• pp.1035-1045
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• 2015

Recent studies in Big Data Analysis are showing promising results, utilizing the main memory for rapid data processing. In-memory computing technology can be highly advantageous when used with high-performing servers having tens of gigabytes of RAM with multi-core processors. The constraint in network in these infrastructure can be lessen by combining in-memory technology with distributed parallel processing. This paper discusses the research in the aforementioned concept applying to a test taxi hailing application without disregard to its underlying RDBMS structure. The application of IMDG technology in the application's backend API without restructuring the database schema yields 6 to 9 times increase in performance in data processing and throughput. Specifically, the change in throughput is very small even with increase in data load processing.

• International Journal of Computer Science & Network Security
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• v.22 no.4
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• pp.89-100
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• 2022

With the advancement in the Internet of things Technology (IoT) cloud computing, billions of physical devices have been interconnected for sharing and collecting data in different applications. Despite many advancements, some latency - specific application in the real world is not feasible due to existing constraints of IoT devices and distance between cloud and IoT devices. In order to address issues of latency sensitive applications, fog computing has been developed that involves the availability of computing and storage resources at the edge of the network near the IoT devices. However, fog computing suffers from many limitations such as heterogeneity, storage capabilities, processing capability, memory limitations etc. Therefore, it requires an adequate task scheduling method for utilizing computing resources optimally at the fog layer. This work presents a comprehensive review of different task scheduling methods in fog computing. It analyses different task scheduling methods developed for a fog computing environment in multiple dimensions and compares them to highlight the advantages and disadvantages of methods. Finally, it presents promising research directions for fellow researchers in the fog computing environment.

• Journal of Information Technology Applications and Management
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• v.12 no.4
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• pp.59-70
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• 2005

Flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional transaction management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. in order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient transaction processing. F2Pl improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process. We also propose a simulation model to show the performance of F2PL. Based on the results of the performance evaluation, we conclude that F2PL scheme outperforms the traditional scheme.

• Journal of Information Processing Systems
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• v.18 no.1
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• pp.159-172
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• 2022

The role of the interconnect network, which connects computing nodes to each other, is important in high-performance computing (HPC) systems. In recent years, the peripheral component interconnect express (PCIe) has become a promising interface as an interconnection network for high-performance and cost-effective HPC systems having the features of non-transparent bridge (NTB) technologies. OpenSHMEM is a programming model for distributed shared memory that supports a partitioned global address space (PGAS). Currently, little work has been done to develop the OpenSHMEM library for PCIe-interconnected HPC systems. This paper introduces a prototype implementation of the OpenSHMEM library through a switchless interconnect network using PCIe NTB to provide a PGAS programming model. In particular, multi-interrupt, multi-thread-based data transfer over the OpenSHMEM shared memory model is applied at the implementation level to reduce the latency and increase the throughput of the switchless ring network system. The implemented OpenSHMEM programming model over the PCIe NTB switchless interconnection network provides a feasible, cost-effective HPC system with a PGAS programming model.

• International journal of advanced smart convergence
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• v.12 no.4
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• pp.164-170
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• 2023

With the recent advances in AI (artificial intelligence) and HPC (high-performance computing) technologies, deep learning is proliferated in various domains of the 4th industrial revolution. As the workload volume of deep learning increasingly grows, analyzing the memory reference characteristics becomes important. In this article, we analyze the memory reference traces of deep learning workloads in comparison with traditional workloads specially focusing on read and write operations. Based on our analysis, we observe some unique characteristics of deep learning memory references that are quite different from traditional workloads. First, when comparing instruction and data references, instruction reference accounts for a little portion in deep learning workloads. Second, when comparing read and write, write reference accounts for a majority of memory references, which is also different from traditional workloads. Third, although write references are dominant, it exhibits low reference skewness compared to traditional workloads. Specifically, the skew factor of write references is small compared to traditional workloads. We expect that the analysis performed in this article will be helpful in efficiently designing memory management systems for deep learning workloads.

• The Journal of Information Technology
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• v.10 no.4
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• pp.41-56
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• 2007

In Digital Computing Environment, volatile information such as register, cache memory, and network information are hard to make certain of a real-time collection because such volatile information are easily modified or disappeared. Thus, a collection of volatile information is one of important step for computer forensics system on ubiquitous computing. In this paper, we propose a volatile information collection module, which collects variable volatile information of server system based on memory mapping in real-time.