• Journal of the Korea Society for Simulation
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• v.4 no.2
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• pp.1-16
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• 1995

The performance of a computer system depends on the system architecture and workload, and the high performance required in many applications can be achieved by the scalability of the system architecture and workload. This paper presents scalable workload, a performance metric of scalable speedup and hierarchical modeling for the scalable computer system as well as the development of the object-oriented simulator spmplC++ Which is an advanced C++ version of the discrete event-driven simulation environment smplE. In addition, this paper presents two examples of applying scalable speedup, hierarchical modeling and simulator smplC++ to analyze the performance effect of the sclcbility in a multiprocessor system and a network-based client/server system.

• Journal of IKEEE
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• v.18 no.3
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• pp.392-397
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• 2014

In this paper, we propose a memory operation system architecture for memory latency penalty reduction in SIMT architecture based stream processor. The proposed architecture applied non-blocking cache architecture to reduce cache miss penalty generated by blocking cache architecture. We verified that the proposed memory operation architecture improve the performance of the stream processor by comparing processing performances of various algorithms. We measured the performance improvement rate that was improved in accordance with the ratio of memory instruction in each algorithm. As a result, we confirmed that the performance of stream processor improves up to minimum 8.2% and maximum 46.5%.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.7C
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• pp.540-547
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• 2008

In this paper, we proposed a new VLSI architecture which can generate computer-generated hologram (CGH) in real-time and implemented to hardware. The modified algorithm for high-performance CGH was introduced and re-analyzed (or designing hardware. from both numerical and visual analysis, the infernal number system of hardware was decided. CGH algorithm and precision analysis enabled to propose a new cell architecture for CGH. The operational sequence was analyzed with the architecture of CGH cell and the characteristics of the modified CGH algorithm, and finally the pipelined architecture and the operational timing were proposed.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.301-301
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• 2004

• Journal of the Korea Society of Computer and Information
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• v.21 no.12
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• pp.115-124
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• 2016

In this paper, a method to generate the extended model automatically on the critical elements in enterprise system based real time distributed architecture as well as the platform specific model(PSM) for Microsoft(MS) .NET platform is proposed. The key ideas of this method are real time distributed architecture should performed with satisfying strict constraints on life cycle of object and response time such as synchronization, transaction and so on, and .NET platform is able to implement functionalities including before mentioned by only specifying Attribute Code and maximizing advantages of MDA. In order to realize the ideas, functionalities which should be considered enterprise system development are specified and these are to be defined in Meta Model and extended UML profile. In addition, after definition of UML profile for .NET specification, by developing and applying these into plug-in of open source MDA tool, and extended models are generated automatically through this tool. Accordingly, by using proposed specification technology, the profile and tools easily and quickly reusable extended model can be generated even though low level of detailed information for functionalities which is considered in .NET platform and real time distributed architecture. In addition, because proposed profile is MOF which is basis of standard extended and applied, UML and MDA tools which observed MOF is reusable.

• ETRI Journal
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• v.20 no.4
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• pp.301-326
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• 1998

In this paper, we have modeled and evaluated a new parallel processing system called Scalable Parallel computer Architecture based on Xbar (SPAX) for commercial applications. SMP systems are widely used as servers for commercial applications; however, they have very limited scalability. SPAX cost-effectively overcomes the SMP limitation by providing both scalability and application portability. To investigate whether the new architecture satisfies the requirements of commercial applications, we have built a system model and a workload model. The results of the simulation study show that the I/O subsystem becomes the major bottleneck. We found that SPAX can still meet the I/O requirement of the OLTP workload as it supports flexible I/O subsystem. We also investigated what will be the next most important bottleneck in SPAX and how to remove it. We found that the newly developed system network called Xcent-Net will not be a bottleneck in the I/O data path. We also show the optimal configuration that is to be considered for system tuning.

• Journal of the Korea Society of Computer and Information
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• v.16 no.9
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• pp.175-183
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• 2011

Data is the kernel of IT. We can apply to other architectures are refer to technology and advanced method. Data architecture is our's native that must be implement ourself. It will suggest to the best method to implement for a sound information system that likes to framework of building because data is not sensitive field of evolution and change of technology. Well implemented data architecture can be effectively management and operation. Also this is easily to implement of enterprise architecture. This paper propose a model of implementation data architecture for enterprise architecture.

• International Journal of Naval Architecture and Ocean Engineering
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• v.12 no.1
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• pp.116-128
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• 2020

In the shipbuilding industry, three-dimensional (3D) templates play a key role in the completeness evaluation of shell plates with a large curvature in the shell-plate fabrication process. Currently, the information of 3D templates from a ship computer-aided design system is limited; thus, manufacturers depend on their experience to produce the templates manually. This results in the inaccuracy of templates in addition to increased production time. Therefore, if the pieces of the 3D templates can be produced automatically with accurate information, the lead time of the fabrication process can be reduced. In this study, we define a new type of template piece and develop methods for extending a boundary template and converting manufacturing information into numerical control machine input. In addition, based on the results of the study, we propose a production automation system for 3D template pieces. This system is expected to reduce the lead time of the fabrication process.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.1081-1087
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• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.