• Title/Summary/Keyword: Computer Language

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The Detection and Correction of Context Dependent Errors of The Predicate using Noun Classes of Selectional Restrictions (선택 제약 명사의 의미 범주 정보를 이용한 용언의 문맥 의존 오류 검사 및 교정)

  • So, Gil-Ja;Kwon, Hyuk-Chul
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.1
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    • pp.25-31
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    • 2014
  • Korean grammar checkers typically detect context-dependent errors by employing heuristic rules; these rules are formulated by language experts and consisted of lexical items. Such grammar checkers, unfortunately, show low recall which is detection ratio of errors in the document. In order to resolve this shortcoming, a new error-decision rule-generalization method that utilizes the existing KorLex thesaurus, the Korean version of Princeton WordNet, is proposed. The method extracts noun classes from KorLex and generalizes error-decision rules from them using the Tree Cut Model and information-theory-based MDL (minimum description length).

Filling the understanding gap of the misplacement of ESL learner's writing placement test (ESL 학습자의 쓰기배치고사상의 오배치에 따른 이해도 차이 연구)

  • Kim, Jung-Tae
    • English Language & Literature Teaching
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    • v.12 no.3
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    • pp.147-166
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    • 2006
  • This study investigates the effect of misplacement in a written Computer-delivered ESL Placement Test (CEPT) context. The study aims to address the following two research questions: a) which scoring rubric features cause the misplacement of ESL learner's writing scores? and b) which scoring rubric features improve ESL learner's writing scores? Thirty-four international examinees took the test and participated in surveys at the University of Illinois. Twelve examinees of them attended the CEPT workshop test. In the workshop test, they carried out self-evaluation on their first essays using a scoring rubric and compared with expert raters' results. After the workshop, the examinees responded to a survey and interview. For the first research question, the results of the survey and interview addressed that the majority disagreed with the raters' rating results. The self-evaluation results also indicated that their misunderstanding of organization feature caused the misplacement. For the second question, the CEPT workshop scores were improved due to the score improvement in the organization feature while the contribution of other features to the total scores was little. Most of the examinees pointed out that a lesson on the scoring rubric enhanced their understanding of the writing features of the rubric so that their placement scores were generally improved.

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Forecasting Load Balancing Method by Prediction Hot Spots in the Shared Web Caching System

  • Jung, Sung-C.;Chong, Kil-T.
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2137-2142
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    • 2003
  • One of the important performance metrics of the World Wide Web is how fast and precise a request from users will be serviced successfully. Shared Web Caching (SWC) is one of the techniques to improve the performance of the network system. In Shared Web Caching Systems, the key issue is on deciding when and where an item is cached, and also how to transfer the correct and reliable information to the users quickly. Such SWC distributes the items to the proxies which have sufficient capacity such as the processing time and the cache sizes. In this study, the Hot Spot Prediction Algorithm (HSPA) has been suggested to improve the consistent hashing algorithm in the point of the load balancing, hit rate with a shorter response time. This method predicts the popular hot spots using a prediction model. The hot spots have been patched to the proper proxies according to the load-balancing algorithm. Also a simulator is developed to utilize the suggested algorithm using PERL language. The computer simulation result proves the performance of the suggested algorithm. The suggested algorithm is tested using the consistent hashing in the point of the load balancing and the hit rate.

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A New Register Transfer Level Synthesis Method for ASIC Design (ASIC 설계를 위한 새로운 레지스터 전송 단계 합성 방법)

  • Lin, Chi-Ho
    • Journal of IKEEE
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    • v.3 no.1 s.4
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    • pp.150-160
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    • 1999
  • This paper presents a new register transfer level synthesis method to overcome the disadvantages of the previous register transfer level synthesis systems. The previous register transfer level synthesis systems first translate from a hardware description language to sequential circuits inadequately. Secondly, the systems separate registers and combinational circuits and then optimize only combinational circuits. This paper describes their disadvantages and then proposes a new method to overcome their shortcomings. This paper also shows the effectiveness of the proposed method by using the proposed method at designing the controller of a surveillance system and the 8-bit signed multiplier.

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STEP-Based Information Exchange for Structural Analysis and Optimization (STEP을 이용한 구조해석 및 최적설계 정보교환)

  • Baek, Ju-Hwan;Min, Seung-Jae
    • Korean Journal of Computational Design and Engineering
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    • v.12 no.1
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    • pp.8-14
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    • 2007
  • In the product design process computer-aided engineering and optimization tolls are widely utilized in order to reduce the total development time and cost. Since several simulation tools are involved in the process, information losses, omissions, or errors are common and the importance of seamless information exchange among the tools has been increased. In this work, ISO STEP standards are adopted to represent the neutral format for structural analysis and optimization. The schema of AP209 defined the information of finite element analysis is used and the new schema is proposed to describe the information of structural optimization based on the STEP methodology. The schema is implemented by EXPRESS, information modeling language, and ST-Developer is employed to generate C++ classes and STEP Rose Library by using the schema denoted. To substantiate the proposed approach, the information access interfaces of the finite element modeling software (FEMAP), structural optimization software(GENESIS) and in-house topology optimization program are developed. Examples are shown to validate the information exchange of finite element analysis and structural optimization using STEP standards.

Design Evaluation of Portable Electronic Products Using AR-Based Interaction and Simulation (증강현실 기반 상호작용과 시뮬레이션을 이용한 휴대용 전자제품의 설계품평)

  • Park, Hyung-Jun;Moon, Hee-Cheol
    • Korean Journal of Computational Design and Engineering
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    • v.13 no.3
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    • pp.209-216
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    • 2008
  • This paper presents a novel approach to design evaluation of portable consumer electronic (PCE) products using augmented reality (AR) based tangible interaction and functional behavior simulation. In the approach, the realistic visualization is acquired by overlaying the rendered image of a PCE product on the real world environment in real-time using computer vision based augmented reality. For tangible user interaction in an AR environment, the user creates input events by touching specified regions of the product-type tangible object with the pointer-type tangible object. For functional behavior simulation, we adopt state transition methodology to capture the functional behavior of the product into a markup language-based information model, and build a finite state machine (FSM) to controls the transition between states of the product based on the information model. The FSM is combined with AR-based tangible objects whose operation in the AR environment facilitates the realistic visualization and functional simulation of the product, and thus realizes faster product design and development. Based on the proposed approach, a product design evaluation system has been developed and applied for the design evaluation of various PCE products with highly encouraging feedbacks from users.

Relational Logic Definition of Articles and Sentences in Korean Building Code for the Automated Building Permit System (인허가관련 설계품질검토 자동화를 위한 건축법규 문장 관계논리에 관한 연구)

  • Kim, Hyunjung;Lee, Jin-Kook
    • Korean Journal of Computational Design and Engineering
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    • v.21 no.4
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    • pp.433-442
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    • 2016
  • This paper aims to define the relational logic of in-between code articles as well as within atomic sentences in Korean Building Code, as an intermediate research and development process for the automated building permit system of Korea. The approach depicted in this paper enables the software developers to figure out the logical relations in order to compose KBimCode and its databases. KBimCode is a computer-readable form of Korean Building Code sentences based on a logic rule-based mechanism. Two types of relational logic definition are described in this paper. First type is a logic definition of relation between code sentences. Due to the complexity of Korean Building code structure that consists of decree, regulation or ordinance, an intensive analysis of sentence relations has been performed. Code sentences have a relation based on delegation or reference each other. Another type is a relational logic definition in a code sentence based on translated atomic sentence(TAS) which is an explicit form of atomic sentence(AS). The analysis has been performed because the natural language has intrinsic ambiguity which hinders interpreting embedded meaning of Building Code. Thus, both analyses have been conducted for capturing accurate meaning of building permit-related requirements as a part of the logic rule-based mechanism.

Extended Entity-Relationship Model for Conceptual Modeling of XML Schema (XML 스키마의 개념적 모델링을 위한 확장된 개체관계 모델)

  • Jung, In-Hwan;Kim, Young-Ung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.15 no.1
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    • pp.157-163
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    • 2015
  • XML has become one of the most influential standard language for representing and exchanging data on internet. However, XML itself has a ability to represent a logical structure for storing and managing data, it is inadequate to use as a conceptual modeling tool because of its complexity for representing the document structures. In this paper, we propose the graphical form of conceptual modeling techniques for representing the structure of the XML schema documents using an extended entity relationship diagram. For this, extended entity relationship model is presented for representing the XML schema structure, transformation rules are presented for transforming extended entity relationship model into XML schema document to show the completeness of the proposed model.

Transformation Methodology to Logical Model from Conceptual Model of XML (XML의 개념적 모델로부터 논리적 모델로의 변환 기법)

  • Kim, Young-Ung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.16 no.6
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    • pp.305-310
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    • 2016
  • In these days, XML is a de facto standard language for representing and exchanging data. In order to define the conceptual model of the XML, we need to define the representation rules expressed in the diagram and propose the transformation algorithm that converts the diagram into a logical model of XML. This paper proposes a transformation methodology for generating a logical model from the conceptual model of the XML. We use CMXML as a conceptual model and generate XML schema definition as a logical model. For this, we define transformation rules and data structures for XML schema, and propose a transformation algorithm.

Parallel LDPC Decoding on a Heterogeneous Platform using OpenCL

  • Hong, Jung-Hyun;Park, Joo-Yul;Chung, Ki-Seok
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.6
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    • pp.2648-2668
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    • 2016
  • Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.