• Journal of Power Electronics
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• v.11 no.1
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• pp.64-73
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• 2011

The stability of PWM rectifiers with a deadbeat current controller is seriously influenced by computation time delays and low-pass filters inserted into the current-sampling circuit. Predictive current control is often adopted to solve this problem. However, grid current predictive precision is affected by many factors such as grid voltage estimated errors, plant model mismatches, dead time and so on. In addition, the predictive current error aggravates the grid current distortion. To improve the grid current predictive precision, an improved deadbeat current controller with a repetitive-control-based observer to predict the grid current is proposed in this paper. The design principle of the proposed observer is given and its stability is discussed. The predictive performance of the observer is also analyzed in the frequency domain. It is shown that the grid predictive error can be decreased with the proposed method in the related bode diagrams. Experimental results show that the proposed method can minimize the current predictive error, improve the current loop robustness and reduce the grid current THD of PWM rectifiers.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.2018-2020
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• 1998

In design of a digital current controller for a 3$\phi$ voltage-source (VS) PWM converter, its conventional model, i.e., stationary or synchronous reference frame model, is used in obtaining its discretized version. It introduces, however, inherent errors since the following practical problems are not taken into consideration: the characteristics of the space vector-based pulsewidth modulation (SVPWM) and the time delays in the process of sampling and computation. In this paper, the new hybrid reference frame model of the 3$\phi$ VS PWM converter is proposed considering these problems. In addition, the direct digital current controller based on this model is designed without any prediction or extrapolation algorithm to compensate the time delay. So the control algorithm is made very simple. The validity of the proposed algorithm is proved by the computer simulation results.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.4
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• pp.175-185
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• 2002

In this paper, a new fully digital current control method of UPS inverter, which is based on an internal model control, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The internal model controller is adopted to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. That is, the average current of filter capacitor is been exactly equal to the reference current with a time lag of two sampling intervals. Therefore, this method has an essentially overshoot free reference-to-output response with a minimum possible rise time. The effectiveness of the proposed control system has been verified by the simulation and experimental respectively. From the simulation and experimental results, the proposed system is achieved the robust characteristics to the calculation time delay and parameter variation as well as very fast dynamic performance, thus it can be effectively applied to the power supply for the critical load.

• Electronics and Telecommunications Trends
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• v.38 no.5
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• pp.34-50
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• 2023

Quantum error correction is a key technology for achieving fault-tolerant quantum computation. Finding the best decoding solution to a single error syndrome pattern counteracting multiple errors is an NP-hard problem. Consequently, error decoding is one of the most expensive processes to protect the information in a logical qubit. Recent research on quantum error decoding has been focused on developing conventional and neural-network-based decoding algorithms to satisfy accuracy, speed, and scalability requirements. Although conventional decoding methods have notably improved accuracy in short codes, they face many challenges regarding speed and scalability in long codes. To overcome such problems, machine learning has been extensively applied to neural-network-based error decoding with meaningful results. Nevertheless, when using neural-network-based decoders alone, the learning cost grows exponentially with the code size. To prevent this problem, hierarchical error decoding has been devised by combining conventional and neural-network-based decoders. In addition, research on quantum error decoding is aimed at reducing the spacetime decoding cost and solving the backlog problem caused by decoding delays when using hardware-implemented decoders in cryogenic environments. We review the latest research trends in decoders for quantum error correction with high accuracy, neural-network-based quantum error decoders with high speed and scalability, and hardware-based quantum error decoders implemented in real qubit operating environments.

• Journal of Platform Technology
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• v.11 no.4
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• pp.71-79
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• 2023

In this paper, we analyze the characteristics of machine learning workloads and, based on them, propose a distributed in-memory caching technique to improve the performance of machine learning workloads. The core of machine learning workload is model training, and model training is a computationally intensive task. Performing machine learning workloads in a Kubernetes-based cloud environment in which the computing framework and storage are separated can effectively allocate resources, but delays can occur because IO must be performed through network communication. In this paper, we propose a distributed in-memory caching technique to improve the performance of machine learning workloads performed in such an environment. In particular, we propose a new method of precaching data required for machine learning workloads into the distributed in-memory cache by considering Kubflow pipelines, a Kubernetes-based machine learning pipeline management tool.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.31 no.5
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• pp.421-427
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• 2013

In general, it can be assumed that the tropospheric effect are removed through double-differencing technique in short-baseline GPS data processing. This means that the high-accuracy positioning can be obtained because various error sources can be eliminated and the number of unknown can be decreased in the adjustment computation procedure. As a consequence, short-baseline data processing is widely used in the fields such as deformation monitoring which require precise positioning. However, short-baseline data processing is limited to achieve high positioning accuracy when the height difference between the reference and the rover station is significant. In this study, the effects of tropospheric delays on the determination of short-baseline is analyzed, which depends on the orientation of baseline. The GPS measurements which include tropospheric effect and measurement noises are generated by simulation, and then rover coordinates are computed by short-baseline data processing technique. The residuals of rover coordinates are analyzed to interpret the tropospheric effect on the positioning. The results show that the magnitudes of the biases in the coordinate residuals increase as the baseline length gets longer. The increasing rate is computed as 0.07cm per meter in baseline length. Therefore, the tropospheric effects should be carefully considered in short-baseline data processing when the significant height difference between the reference and rover is observed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.7
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• pp.113-121
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• 2005

In this paper, a constant output power supply system for ozonizer is proposed to remove the noise of ozonizer and control the output of ozonizer using feedback control. The proposed system is based on the rouble control loop such as the outer voltage control loop and inner current control loop. In the proposed system overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.2
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• pp.116-127
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• 2003

In this paper, a new fully digital control method for UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an Internal model controller The Internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the simulation and experimental results respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.1-11
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• 2007

In this paper, a new fully digital control method for UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the simulation and experimental results respectively.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1964-1980
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• 2016

This paper presents a new simplified harmonics extraction algorithm based on the synchronous reference frame (SRF) for an indirect current controlled (ICC) three-level neutral point diode clamped (NPC) inverter-based shunt active power filter (SAPF). The shunt APF is widely accepted as one of the most effective current harmonics mitigation tools due to its superior adaptability in dynamic state conditions. In its controller, the SRF algorithm which is derived based on the direct-quadrature (DQ) theory has played a significant role as a harmonics extraction algorithm due to its simple implementation features. However, it suffers from significant delays due to its dependency on a numerical filter and unnecessary computation workloads. Moreover, the algorithm is mostly implemented for the direct current controlled (DCC) based SAPF which operates based on a non-sinusoidal reference current. This degrades the mitigation performances since the DCC based operation does not possess exact information on the actual source current which suffers from switching ripples problems. Therefore, three major improvements are introduced which include the development of a mathematical based fundamental component identifier to replace the numerical filter, the removal of redundant features, and the generation of a sinusoidal reference current. The proposed algorithm is developed and evaluated in MATLAB / Simulink. A laboratory prototype utilizing a TMS320F28335 digital signal processor (DSP) is also implemented to validate effectiveness of the proposed algorithm. Both simulation and experimental results are presented. They show significant improvements in terms of total harmonic distortion (THD) and dynamic response when compared to a conventional SRF algorithm.