• Proceedings of the Korean Institute of Building Construction Conference
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• 2012.05a
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• pp.341-343
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• 2012

This study introduces a method for computation of process and operation gap in the specific construction operation(i.e., RC frame construction applying a block-grouping scheme) using CYCLONE-based simulation modeling and analysis technique. Since uncertainty of construction environment exists, a thoughtful production planning is required to effectively deal with a risk resulting in schedule delay in advance. This study presents the concepts of a time delay occurred in a process level and operation level in a operation model, and a method of measuring gap-times in each level while the simulation progresses. It helps a site manager to decide how many segmentation in a construction block is suitable for eliminating unproductive time-delays under the constrained resources (e.g., laborer, equipment). A case study presents a network model representing a three segmented RC frame work, and result obtained from the simulation experiment.

• Journal of Power Electronics
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• v.13 no.4
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• pp.600-608
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• 2013

This paper analyzes the effect of the admittance component for the digitally controlled single-phase bridgeless power factor correction (PFC) converter. To do this, it is shown how the digital delay effects such as the digital pulse-width modulation (DPWM) and the computation delays restrict the bandwidth of the converter. After that, the admittance effect of the entire digital control system is analyzed when the bridgeless PFC converter which has the limited bandwidth is connected to the grid. From this, the waveform distortion of the input current is explained and the compensation method for the admittance component is suggested to improve the quality of the input current. Both the simulations and the experiments are performed to verify the analyses taken in this paper for the 1 kW bridgeless PFC converter prototype.

• Management Science and Financial Engineering
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• v.5 no.1
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• pp.1-25
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• 1999

There is a worldwide trend to automate the handling operations in port container terminals in an effort to improve productivity and reduce labor cost. This study iscusses how to apply an AGV(automated guided vehicle) system to the handling of containers in the yard of a port container ter-minal. The main issue of this paper is how to assign tasks of container delivery to AGVs during ship operations in an automated port container terminal. A dual-cycle operation is assumed in which the loading and the discharging operation can be performed alternately. Mixed integer linear program-ming formulations are suggested for the dispatching problem. The completion time of all the dis-charging and loading operations by a quayside crane is minimized, and the minimization of the total travel time of AGVs is also considered as a secondary objective. A heuristic method using useful properties of the dispatching problem is suggested to reduce the computational time. The perfor-mance of the heuristic algorithm is evaluated in light of solution quality and computation time.

• Journal of Communications and Networks
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• v.16 no.4
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• pp.436-446
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• 2014

The high intensity of research and modeling in fields of mathematics, physics, biology and chemistry requires new computing resources. For the big computational complexity of such tasks computing time is large and costly. The most efficient way to increase efficiency is to adopt parallel principles. Purpose of this paper is to present the issue of parallel computing with emphasis on the analysis of parallel systems, the impact of communication delays on their efficiency and on overall execution time. Paper focuses is on finite algorithms for solving systems of linear equations, namely the matrix manipulation (Gauss elimination method, GEM). Algorithms are designed for architectures with shared memory (open multiprocessing, openMP), distributed-memory (message passing interface, MPI) and for their combination (MPI + openMP). The properties of the algorithms were analytically determined and they were experimentally verified. The conclusions are drawn for theory and practice.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.346-351
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• 1998

In design of a digital current controller for a 3-phase (3 ) voltage-source (VS) PWM converter, its conventional model, i.e., stationary or synchronous reference frame model, is used in obtaining its discretized version. It introduces, however, inherent errors since the following practical problems are not taken into consideration: the characteristics of the space vector-based pulse-width modulation (SVPWM) and the time delays in the process of sampling and computation. In this paper, the new hybrid reference frame model of the 3 VS PWM converter is proposed considering these problems. In addition, the direct digital current controller based on this model is designed without any prediction or extrapolation algorithm to compensate the time delay. So the control algorithm is made very simple. It represents no steady-state error in input current control and has the optimized transient responses. The validity of the proposed algorithm is proved by the computer simulation and experimental results.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.2
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• pp.74-81
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• 2002

In general, a multipath generator consists of a time delay generator, phase rotator, and amplitude attenuator, and is implemented mostly in an analog manner. Analog, or partially analog versions of a multipath generator is disadvantageous in that they may suffer from problems associated with component aging and adjustment, signal fidelity degradation stemming from repeated A/D and D/A conversion use of high frequency to achieve fine i.e., subsample fractional tin delays. This paper presents the design and implementation methodology of a full digital multipath generator which can be used in performance evaluations of digital terrestrial television as well as communications, receivers. In particular, an efficient practical method is proposed which can achieve both integer and fractional time delays simultaneously, without placing restrictions on the allowable system master clock frequency. The proposed algorithm lends itself to minimizing hardware implementation cost by relegating some fixed put of the computation involved to an IBM PC. The proposed multipath generator occupies only a single digital board space, and its experimental results are provided to corroborate the proposed implementation methodology.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.91-100
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• 2016

In FPGA-based real-time image warping systems, image caches are utilized for fast readout of image pixel data and reduction of memory access rate. However, a cache algorithm for a general computer system is not suitable for real-time performance because of time delays from cache misses and on-line computation complexity. In this paper, a simple image cache algorithm is presented for a FPGA-based real-time image warping system. Considering that pixel data access sequence is determined from the 2D coordinate transformation and repeated identically at every image frame, a cache load sequence is off-line programmed to guarantee no cache miss condition, and reduced on-line computation results in a simple cache controller. An overall system structure using a FPGA is presented, and experimental results are provided to show accuracy and validity of the proposed cache algorithm.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1221-1245
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• 2014

Real-time hybrid simulation (RTHS) is a promising cyber-physical technique used in the experimental evaluation of civil infrastructure systems subject to dynamic loading. In RTHS, the response of a structural system is simulated by partitioning it into physical and numerical substructures, and coupling at the interface is achieved by enforcing equilibrium and compatibility in real-time. The choice of partitioning parameters will influence the overall success of the experiment. In addition, due to the dynamics of the transfer system, communication and computation delays, the feedback force signals are dependent on the system state subject to delay. Thus, the transfer system dynamics must be accommodated by appropriate actuator controllers. In light of this, guidelines should be established to facilitate successful RTHS and clearly specify: (i) the minimum requirements of the transfer system control, (ii) the minimum required sampling frequency, and (iii) the most effective ways to stabilize an unstable simulation due to the limitations of the available transfer system. The objective of this paper is to establish a stability switch criterion due to systematic experimental errors. The RTHS stability switch criterion will provide a basis for the partitioning and design of successful RTHS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.10
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• pp.1487-1493
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• 2013

A new simple control method for active power filter, which can realize the complete compensation of harmonics is proposed. In the proposed scheme, a model-based digital current control strategy is presented. The proposed control system is designed and implemented in a form referred to as internal model control structure. This method provides a convenient way for parameterizing the controller in term of the nominal system model, including time-delays. As a result, the resulting controller parameters are directly set based on the power circuit parameters, which make tuning of the controllers straightforward task. In the proposed control algorithm, overshoots and oscillations due to the computation time delay is prevented by explicit incorporating of the delay in the controller transfer function. In addition, a new compensating current reference generator employing resonance model implemented by a DSP(Digital Signal Processor) is introduced. Resonance model has an infinite gain at resonant frequency, and it exhibits a band-pass filter. Consequently, the difference between the instantaneous load current and the output of this model is the current reference signal for the harmonic compensation.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1322-1333
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• 2014

To track the sinusoidal current under stationary frame and suppress the effects of low-order grid harmonics, the multi-resonant quasi-proportional plus resonant (PR) controller has been extensively used for digitally controlled LCL-type pulse-width modulation (PWM) converters with capacitor-current-feedback active damping. However, designing the controller is difficult because of its high order and large number of parameters. Moreover, the computation and PWM delays of the digitally controlled system significantly affect damping performance. In this study, the delay effect is analyzed by using the Nyquist diagrams and the system stability constraint condition can be obtained based on the Nyquist stability criterion. Moreover, impact analysis of the control parameters on the current loop performance, that is, steady-state error and stability margin, identifies that different control parameters play different decisive roles in current loop performance. Based on the analysis, a simplified controller design method based on the system specifications is proposed. Following the method, two design examples are given, and the experimental results verify the practicability and feasibility of the proposed design method.