• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.5
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• pp.83-97
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• 1998

This paper developes an integrated environment CAD system that can design and implement an accurate and cost-effective FLC automatically. For doing this, an integrated development environment (IDE) (called FADIS; FLC Automatic Design and Implementation Station) is built by the seemless coupling of many existing. CAD tools in an attempt to the FADIS performs various functions such that (1) i~utomatically generate the VHDL components appropriate for the proposed FLC architecture from the various design parameters (2) simulate the generated VHDL code on the Synopsys's VHDL Simulator, (3) automatically compiler, (4) generate the optimized, placed, and routed rawbit files from the synthesized modules by Xilinx's XactStep 6.0, (5) translate the rawbit files into the downloadable ex- [:cution reconfigurable FPGA board (VCC's EVCI), and (7) continuously monitor the control status graphically by communicating the FLC with the controlled target via S-bus. The developed FADIS is tested for its validity by carrying out the overall procedures of designing and implementing the FLC required for the truck-backer upper control, the reduction of control execution time due to the controller's FPGA implementation is verified by comparing with other implementations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.723-736
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• 1999

Code optimization phase in a compiler are very important because the phase reduces the running time and the storage size of machine codes. I developed flow analyzers and optimizers on intermediate codes. The flow analyzers generate control-flow and data-flow information. The optimizers transform the intermediate codes into the improved codes using this information. This paper describes the development of flow analyzers and optimizers. I also examined the execution performance, the cost and the dependency of each optimization.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.216-220
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• 2010

본 연구는 앞으로 개발될, 혹은 현재 개발이 진행중인 16 비트 CPU를 위한 C 컴파일러를 개발하고자 한다. 본 연구는 다양하고 특별한 용도의 새로운 CPU를 위한 새로운 C 컴파일러들을 보다 쉽게 개발할 수 있게 한다. 공개 소프트웨어인 GNU C 컴파일러 생성기를 사용하여 새로운 CPU의 기능들을 명세하고, 기계 의존 원시 파일들을 수정함으로서 새로운 컴파일러를 개발할 수 있다. 개발된 컴파일러는 16 비트 CPU가 지원하는 16 비트 산술 연산 뿐만 아니라, 16 비트 CPU가 지원하지 않는 16 비트 산술 연산, 32 비트 Data Movement 연산, 32 비트 산술 연산, 32 비트 floating point 연산까지 가능하다. 그러나, 배열, 포인터, 구조체 등과 같은 고급 기능들을 지원하기 위해서는 더 많은 연구가 필요하다.

• Journal of the Korean Society of Industry Convergence
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• v.5 no.2
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• pp.141-146
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• 2002

Stereolithography is the best known as rapid prototyping system. It uses the STL format data which is generated from CAD system. In this study, One of the main function of this developed CAM system deals with shape modification which divide a shape into two parts or more. The cross section of a STL part by a z-level is composed with nested or single polygonal closed loop. In order to make RP product, closed loops must fill with triangular facets from SSET and recover sliced triangular facets which is located normal direction to the cross sectional plane. The system is development by using Visuall C++ compiler in the environment of pentium PC. Operating system is Windows NT workstaion from Micro-Soft.

• Journal of Industrial Technology
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• v.22 no.B
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• pp.251-260
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• 2002

In this thesis, a three degrees of freedom robot, which is able to provide sufficient precision for various robot researches, has been developed. The cable mechanism is used as a basic transmission of robot joints. Based on an optimal design strategy, link and joint parameters are determined and then overall geometry of the robot is designed. As an architecture of robot control, real time control system using real time linux and RtiC-Lab(Real Time Controls Laboratory) is developed. This system, written in C and based on Linux O/S, includes text editor, compiler, downloader, and real time plotter running in host computer for developing control purpose. Using these hardware and software, simple PD position control is implemented, the results shows the effectiveness of the system.

• Proceedings of the KIEE Conference
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• 1999.07b
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• pp.927-929
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• 1999

In this research a real-time control system was developed without program codings during control system designing procedures. On the Simulink window control system is designed in the form of block diagrams, program codes are produced automatically with the real time workshop package, then C-compiler compiles the program codes. With this automatic real-time program producing mechanism rapid prototyping is realized. To show effectiveness of the proposed system designing scheme a DSP-based DC motor speed control system was constructed and PI and Fuzzy control methods were implemented.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.413-418
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• 1987

The software developed for the large scale Programmable Controller consists of the programmer's S/W, the Controller's S/W the RBC's (Remote Base Controller's) S/W and the Analog's S/W. The programmer's S/W, running on the Programmer, includes the editor, the compiler, the communication program, and some other programs for easy use. The Controller S/W, which requires the fast scanning time, consists of the BTI( Block Type Instruction) solving program, the timer service routine, the i/o update program, the communication program and etc. The RBC's S/W includes the communication program, the error recovery program and the i/o processing program. The analog S/W, controlled by the Programmer, includes the PID program. The data communication between the Programmer and the Controller the Controller and the RBC, and the RBC and the Analog are developed.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.217-221
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• 2002

In this research a Matlab/Simulink/RTW - based on the realtime control system was developed for an induction motor vector control. On the Simulink window, the control system is designed In the form of block diagrams, program codes are produced automatically with the RTW(Real Time Workshop), then a DSP c compiler complies the program codes.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.439-442
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• 2009

본 연구는 16 비트 CPU를 위한 새로운 C 컴파일러를 개발하고자 한다. 새로운 ASIC 프로세서가 특정 용도로 설계되었을 때 그 CPU를 위한 새로운 컴파일러의 개발이 필요하다. 공개 소프트웨어인 GNU C 컴파일러를 사용하여 기계 의존 원시 파일들을 수정함으로서 새로운 컴파일러를 개발할 수 있다. 개발된 컴파일러는 단지 기계어에 의해 처리될 수 있는 기능들만 지원할 수 있기 때문에 곱 셈, 나눗셈, 부동소수점 처리등과 같은 기능들을 지원하기 위해서는 더 많은 연구가 필요하다. 완전한 컴파일러가 개발된 후에는 새로운 CPU에서 실행될 수 있는 응용 프로그램의 개발이 필요하다. 본 연구에 의해서 앞으로 개발될 여러 가지 다른 용도의 CPU를 위한 컴파일러들이 쉽게 개발될 수 있을 것이다.