• Journal of Power Electronics
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• v.7 no.3
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• pp.238-245
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• 2007

This paper considers the problem of regulating the output voltage of a current doubler rectified asymmetric half-bridge (CDRAHB) DC/DC converter via fuzzy integral control. First, we model the dynamic characteristics of the CDRAHB converter with the state-space averaging method, and after introducing an additional integral state of the output regulation error, we obtain the Takagi-Sugeno (TS) fuzzy model for the augmented system. Second, the concept of parallel distributed compensation is applied to the design of the TS fuzzy integral controller, in which the state feedback gains are obtained by solving the linear matrix inequalities (LMIs). Finally, numerical simulations of the considered design method are compared to those of the conventional method, in which a compensated error amplifier is designed for the stability of the feedback control loop.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.11
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• pp.1-8
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• 1997

In this paper, we propose a new method for the improvement of linearizing and adaptive convergence charateristics of the feedforward linear power amplifier. In this circuit, errors at the signal cancellation stage can be compensated at the error cancellation stage and the overall linearizaton and adaptation characteristics of the linear amplifier are improved. The broadband characteristics and linearizing capability are improved without increasing the complexity of circuits and the signal processing structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.948-953
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• 2017

When using a high-power amplifier(HPA) for high-speed communication, the nonlinear characteristics of the HPA deteriorate power efficiency, bit error rate(BER) performance, and spectral efficiency. Because it is inevitable to use the HPA to obtain sufficient transmission power for high-speed communication, it is necessary to compensate for nonlinearity of the HPA by using a predistorter. In this study, a predistorter was used to compensate for the nonlinearity of the HPA, and the nonlinear distortion was compensated using the predistorter. Simulation results show that the compensation of the nonlinearity of the HPA using the predistorter achieves a BER performance similar to that of an ideal linear amplifier, and that the spectral mask is also satisfied.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.10
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• pp.595-600
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• 2002

This paper presents the analyzed results of dynamic characteristics including steady state characteristics of the boost input type ZVS converter using the active clamp circuit by the state space averaging method. From the results, it can be seen that the converter has the 5th order transfer functions and the stable closed loop characteristic is obtained by using the compensated error amplifier with 2-pole and 1-zero. The validity of all analyzed results are verified by measurement.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.28-35
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• 2006

This paper presents a new 3.3-1 V synchronous buck DC/DC converter that employs CMOS operational transconductance amplifiers (OTAs) as circuit-building blocks. An error amplifier OTA in a PWM circuit is compensated for to improve temperature stability. The temperature coefficient of the transconductance gain of the compensated OTA is less than $150\;ppm/^{\circ}C\;over\;0-100^{\circ}C$. The HSPICE simulation results of the $0.3{\mu}m$ standard CMOS technology show that the efficiency of the proposed converter is as high as 80% in the load current range of 40-125 mA. These results show that the proposed converter is adequate for use in battery-operated systems.