• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.251-256
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• 2004

A stable reference voltage generator is necessary to the infrared image signal readout circuit(ROIC) to improve noise characteristics in comparison with signals originated from infrared devices, that is, to gain good images. In this study, bandgap reference circuit operating at cryogenic temperature of 77K for Infrared image ROIC(readout integrated circuit) was propose. Most of bandgap reference circuits which are presented so far operate at room temperature, and they are not suitable for infrared image ROIC operating at liquid nitrogen temperature, 77K. To design bandgap reference circuit operating at cryogenic temperature, the parameter characteristics of used devices as temperature change are seen, and then bandgap reference circuit is proposed with considering such characteristics. It demonstrates practical use possibility through taking measurements and estimations.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.705-706
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• 2006

Generally Short Circuit Test of transformers are tested according to IEEE std C57.12.00-2000, IEC 60076-5(2000-07), ES148(1998.6.26) or KS C4309(2003). But ES148(1998.6.26) is same as IEEE std C57. 12.00-2000 and KS C4309(2003) is revising coincidence with IEC 60076-5(2000-07). On this study condition of the transformers before short circuit test, calculation method for test current peak value, tolerance on the asymmetrical peak and r.m.s value, short circuit testing procedure, number of short circuit test, duration short circuit test, and detection of faults and evaluation of short circuit test result will be compared with ANSI and IEC.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• Journal of the Korean Society of Safety
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• v.29 no.4
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• pp.54-60
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• 2014

This paper describes electric shock accidents on a 4.16 kV class circuit breaker for power plant. Electric shock accidents mostly involve damage of human life, in comparison with electrical fire, rate of human death tend to be higher in electric shock accidents. Specially, in a high voltage facilities rate of human death comprised about 43.7% by electric shock accidents. If electric shock accidents happen in a 4.16 kV class circuit breaker for power plant, then the power plant discontinue power production. Electric shock accidents in a power plant have a great ripple effect such as an electric power shortage. In this paper, we analyzed electric shock accidents on a 4.16 kV class circuit breaker for power plant. From the analysis results, we confirmed a cause of electric shock accidents on a 4.16 kV class circuit breaker, it happened by defect of interlock equipment or occurrence of breakdown between first feeder contactor and shielding plate. In order to reduce electric shock accidents on a 4.16 kV class circuit breaker, the power plant should consider improvement of interlock equipment and insulation of feeder contactor in circuit breaker.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.3
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• pp.267-271
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• 2005

This paper deals with two kinds of novel shape switched reluctance motors (SRM) with magnetic barriers in order to improve operating performances of prototype. The magnetic barriers make rotor poles more saturated, and consequently inductance profiles are distorted. The changed inductance affects input current shape and eventually torque characteristics. In order to analyze the complicated flux pattern of the SRM with magnetic barriers and its terminal characteristics simultaneously, coupled field circuit modeling method is used. The finite element method is used to model the nonlinear magnetic field, and coupled to the circuit model of the SRM overall system. After experimental results are presented to prove the accuracy of the method, the several analysis results are compared, and the improved rotor shape is presented.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.694-696
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• 2002

Transformers together with all equipment and accessories shall be designed and constructed to withstand the mechanical and thermal stresses produced by external short circuit which include three phase, single line-to-ground, double line-to-ground and line-to-line faults etc. Generally the Short Circuit Test of transformers is tested according to the ANSI/IEEE, IEC/JEC, KS etc, in domestic. In this study, it will be showed and compared the difference of symmetrical current for short circuit test of a Pad -mounted transformer according to with ANSI /IEEE and IEC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.401-410
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• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.256-259
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• 2006

Comparison of one two-path single energy recovery circuit for plasma display panel (PDP) is shown in this paper. A single energy recovery circuit (SERC) is proposed to reduce cost for manufacturing PDP and there are two ways, one and two-path, in driving this circuit. Compared with one-path SERC, there are low power consumption, low surge current and high performance in two-path SERC. The results will be shown with 42-inch HD panel.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.1
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• pp.15-22
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• 1974

A new ternary full adder using the current controlled negative-resistance circuit is described. The full adder is constructed from the modified-half-adder which was devised by making use of a negative resistance circuit. This full adder makes the number of its gates decrease and makes its own speed increase in comparison with the full adders which had been introduced previously. It is convenient to construct to the integrated circuit because transistor, SBD(Schottky Barrier Diode) and resistors were used as the circuit elements.