• Journal of Power Electronics
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• v.18 no.1
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• pp.70-80
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• 2018

A novel strategy based on a zero common mode voltage pulse-width modulation (ZCMV-PWM) technique and zero-sequence circulating current (ZSCC) feedback control is proposed in this study to eliminate ZSCCs between three-level neutral point clamped (NPC) voltage source inverters, with common AC and DC buses, that are operating in parallel. First, an equivalent model of ZSCC in a three-phase three-level NPC inverter paralleled system is developed. Second, on the basis of the analysis of the excitation source of ZSCCs, i.e., the difference in common mode voltages (CMVs) between paralleled inverters, the ZCMV-PWM method is presented to reduce CMVs, and a simple electric circuit is adopted to control ZSCCs and neutral point potential. Finally, simulation and experiment are conducted to illustrate effectiveness of the proposed strategy. Results show that ZSCCs between paralleled inverters can be eliminated effectively under steady and dynamic states. Moreover, the proposed strategy exhibits the advantage of not requiring carrier synchronization. It can be utilized in inverters with different types of filter.

• The Mathematical Education
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• v.39 no.2
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• pp.151-166
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• 2000

The purpose of this study is to understand what two models of SOLO taxonomy and van Hiele theory suggest and find out what relation there is between the category system of the SOLO taxonomy and the thinking level of the van Hiele theory. The van Hiele theory describes in line of ranking level so that it may increase the teaching effects by putting together a class, which takes into consideration the students thoughts. The SOLO taxonomy focused on the response mode of the students rather than the thinking level or the developmental stage of them to pursuit the method that can describe the students understanding in depth quality-wise. Although the SOLO taxonomy and the van Hiele model seem to have different form and character from outside in terms of their goals, a closer examination reveals that the two stances have much in common and that the models are complementary. Although the van Hiele placed more focus on the thoughts, because the conclusion was based on the students responses, the van Hiele theory can be interpreted within the structure identified in the SOLO model. In this study, we have tried to understand how the response structure form the SOLO taxonomy and the thinking level of the van Hiele theory are related, based on the studies of Pegg and Davery1998). If you briefly look at them, there are following corresponding relation between the SOLO taxonomy and the van Hiele theory. a) The relational level(R) in iconic moe is van Hiele level 1. b) The multisturctural level(M$_2$) in the second cycle of concrete-symbolic mode is van Hiel level 2. c) The relation level(R$_2$) in the second cycle of concrete-symbolic mode is van Hiele level 3. d) The unistructural level(U$_2$) in the second cycle of formal mode is van Hiele level 4. e) The postformal mode is van Hiele levle 5. Though it would be difficult to conclude that these correspondences were perfectly done, if you look at their relation, you can see that the learning process of the students were not carried out uniformly. Therefore, by studying the students response structure, using the SOLO taxonomy, and identifying the learning cycle and understand the geometrical concept more in depth.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1458-1469
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• 2018

This paper proposes a novel common-mode voltage (CMV) elimination (CMV-EL) method based on model predictive control (MPC) to eliminate CMV for three-level T-type inverters (3LT2Is). In the proposed MPC method, only six medium and one zero voltage vectors (VVs) (6MV1Z) that generate zero CMV are considered as candidates to perform the MPC. Moreover, the influence of dead-time effects on the CMV of the MPC-based 6MV1Z method is investigated, and the candidate VVs are redesigned by pre-excluding the VVs that will cause CMV fluctuations during the dead time from 6MV1Z. Only three or five VVs are included to perform optimization in every control period, which can significantly reduce the computational complexity. Thus, a small control period can be implemented in the practical applications to achieve improved grid current performance. With the proposed CMV-EL method, the CMV of the $3LT^2Is$ can be effectively eliminated. In addition, the proposed CMV-EL method can balance the neutral point potentials (NPPs) and yield satisfactory performance for grid current tracking in steady and dynamic states. Simulation and experimental results are presented to verify the effectiveness of the proposed method.

• The Journal of the Korea Contents Association
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• v.6 no.3
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• pp.38-45
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• 2006

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for a LCD driver IC. We apply two data to the proposed DLVDS circuit as inputs. Then, the transmitter converts two inputs to two kinds of fully differential signals. In this circuit, two transmission lines are sufficient to transfer two inputs while keeping the LVDS feature. However, the circuit has a common mode bias fluctuation due to difference of the input bias and the reference bias. We compensate the common mode bias fluctuation using a feedback circuit of the current source bias. The receiver recovers the original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25{\mu}m$ CMOS technology. The simulation results of proposed circuit shows 1-Gbps/2-line data rate and 35mW power consumption at 2.5V supply voltage, respectively.

• Journal of Power Electronics
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• v.17 no.3
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• pp.641-652
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• 2017

This paper proposes a cost-effective topology to drive a three-phase open-end load based on a five-leg indirect matrix converter (IMC) and a space vector modulation (SVM) method. By sharing an inverter leg with two load terminals, the proposed topology can reduce the number of power switches when compared to topologies based on a direct matrix converter or a six-leg IMC. The new SVM method uses only the active vectors that do not produce common-mode voltage (CMV), which results in zero CMV across the load phase and significantly reduces the peak value of the CMV at the load terminal. Furthermore, the proposed drive system can increase the voltage transfer ratio up to 1.5 and provide a superior performance in terms of an output line-to-line voltage with a three-level pulse-width modulation waveform. Simulation and experimental results are given to verify the effectiveness of the proposed topology and the new SVM method.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.5
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• pp.336-344
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• 2018

This study proposes a new PWM method for leakage current reduction and neutral point (NP) current control in three-phase three-level converter employed in bipolar DC distribution systems. The proposed PWM method uses medium vectors only when there is no need to control the NP current. Thus, common mode voltages are held constant to realize zero leakage current. Some space vectors that produce low-frequency common mode voltages are employed to minimize leakage currents when the average NP current needs to be a positive or negative value. The proposed space vector PWM is implemented based on barycentric coordinate. The validity of the proposed PWM method is verified by simulations and experiments.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1288-1291
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• 2002

In this paper, we present a design of mpeg-4 video codec chip to reduce the power consumption using frame level clock gating and motion estimation skip scheme. It performs 30 grames/s of codec (encoding and decoding) mode with quarter-common intermediate format(QCIF) at 27MHz. A novel low-power techniques were implemented in architectural level, which is 35% of the power dissipation for a conventional CMOS design. This chip performs MPEG-4 Simple Profile Level 2(Simple@L2) and H.263 base mode. Its contains 388,885 gates, 662k bits memory, and the chip size was 9.7 mm x 9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.

• Journal of Power Electronics
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• v.11 no.4
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• pp.512-519
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• 2011

This paper gives a detailed analysis of the direct torque control (DTC) strategy in a five-level drive and proposes a 24-sector switching table. The known problems in low-voltage drives such as bearings currents and an overvoltage phenomenon which leads to premature failure are reviewed and the occurrence of these problems in medium voltage drives has been investigated. Then a solutions to these problems is presented and the switching table to deal with these problems is modified. Simulation and experimental results on a 3kVA prototype confirm the proposed solution. In implementing the above strategy a TMS320F2812 is used.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.287-288
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• 2014

본 논문에서는 3레벨 4레그 컨버터에서 커먼 모드 전압(Common-mode Voltage, CMV)을 저감하기 위한 삼각파 비교 전압 변조 기법을 제안하였다. 제안한 PWM 방법은 매우 직관적이고, DSP 제어 시스템에서 쉽게 구현할 수 있다. SVPWM, SPWM의 스위칭 패턴 분석을 통하여 CMV 저감을 위한 4번째 레그(f상)의 극 전압 패턴을 제안하였고, 해당하는 f상 극 전압의 합성을 위하여, f상 양/음의 극 전압 지령 값을 계산하였다. 또한 a, b, c상 전압 왜곡을 막기 위한 옵셋 전압을 유도하였다. 제안한 PWM 방법의 유효성은 모의실험과 실험 결과를 통하여 검증되었다. 제안된 방법에서 CMV의 첨두치 및 스위칭 수는 SVPWM 방법에 비하여 각각 33%, 25%로 대폭 감소하였다.

• Journal of electromagnetic engineering and science
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• v.4 no.4
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• pp.168-174
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• 2004

A bandwidth-enhanced and phase noise-improved differential LC-tank VCO is proposed in this paper. By connecting the varactors to the bases of the cross-coupled transistors of the proposed LC-tank VCO, its input negative resistance has been widened. Also, the feedback capacitor Cc in the cross-coupling path of the proposed LC-tank VCO attenuates the output common-mode level modulated by the low-frequency noise because the modulated common-mode level jitters the varactor bias point and degrades phase noise. Compared with the fabricated conventional LC-tank VCO, the proposed LC-tank VCO demonstrates $200\;\%$ enhancement in tuning range, and 6 - dB improvement in phase noise at 6 MHz offset frequency from 5.4-GHz carrier. We achieved the phase noise of - 106 dBc/Hz at 6 MHz offset, and $10\;\%$ tuning range from the proposed LC-tank VCO. The proposed LC-tank VCO consumes 12 mA at 2.5 V supply voltage.