• 한국농촌건축학회논문집
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• 제14권3호
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• pp.51-60
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• 2012

Gwangju Metropolitan City has implemented a creative regeneration project of Gwangju Folly in the site of Gwangju-eup Fortress as part of the Gwangju Design Biennale by inviting well-known international architects. This study examined and analyzed the characteristics of location, place, and space through actual survey. The results were as follows. Gwangju Folly were mainly located at the four gates and corners of Gwangju-eup Fortress, main entrances of Asia Culture Complex, and historical places where the May 18 Democratization Movement occurred. The common place of Gwangju Folly was a footpath and common location types were the full location of footpath width and the partial location of footpath width. For the spatial types of Gwangju Folly, the practical type which people can stay was the most common(2/3). In the partial location of footpath width, the type which people take a rest and look out over the surroundings accounted for a half. In the full location of footpath width, the gate type which people pass accounted for 2/5. However, as footpath width was minimum for walking, both partial and full occupation types were narrow in place. It influenced the image of Gwangju Folly. Gwangju Folly did not play as a figure and show architects' intentions clearly because of their narrow locations. Therefore, it is very necessary to make a plan to maintain places so that Gwangju Folly do not have a cramped image and architects' intentions become clear with citizens' cultural competence. Also, urban property which creates the identity and attraction of Gwangju continuously should be settled down through helping citizens recognize the intention and value of artistic works.

• 한국산업정보학회논문지
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• 제7권5호
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• pp.147-153
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• 2002

GHz에서 동작하는 초미세 MOSFET의 BSIM3 MOSFET 모델에 연결하여 사용할 수 있는 기판 회로망 모델과 그에 따른 물리적 의미를 가지는 직접 파라미터 추출법이 제안되었다. 제안된 기판 회로망에는 관례적인 저항과 링-형태의 기판콘택에 의해 생성된 단일의 인덕터가 포함되었다. 모델 파라미터는 최적화 과정 없이 단절된 게이트와 공통-벌크 구성을 갖는 MOS 트랜지스터에서 측정된 S-파라미터로부터 추출되었다. 제안된 모델링 기술은 다양한 크기의 MOS 트랜지스터에 적용되었고, 30GHz까지 그 타당성이 검증되었다.

• 제어로봇시스템학회논문지
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• 제6권2호
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• 한국산학기술학회논문지
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• 제12권5호
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• pp.2317-2321
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• 2011

본 논문에서는 기존 암호알고리즘과 호환성을 갖는 비밀키 암호알고리즘에 기반을 둔 새로운 데이터 암호알고리즘을 제안 하였다. 그러므로 스마트 카드에 적합한 새로운 암호 블록을 설계하고 검증하는데 범용 Synopsys로 설계하였고 40MHz의 시스템 속도환경에서 Altera MAX+PlusII툴로 모의실험 및 검증한 결과 단일 라운드로 640Mbps의 데이터 처리율을 확인하였다. 따라서, 제안된 암호시스템에 적용할 경우 실시간 정보 보안에 적용할 수 있다고 사료된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
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• pp.520-521
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• 2008

This paper describes a low voltage, low-power CMOS buck DC/DC converter, which has a simple common-gate current sensing circuit. It consumes low power because it includes less transistors than other converters which use operational amplifiers for current sensing. The designed DC-DC converter is fabricated in a 0.18um CMOS technology. A maximum efficiency of 88% has been obtained with the proposed circuit. It has $2V{\sim}3.7V$ input voltage range, $1V{\sim}2.5V$ output voltage range and maximum output current of 1000mA.

• 한국통신학회논문지
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• 제22권11호
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.

• 한국통신학회논문지
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• 제26권10B호
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• pp.1475-1481
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• 2001

무선 통신을 위한 전력 증폭기를 0.25$\mu\textrm{m}$ CMOS 공정으로 구현하였다. 전력 효율을 증가시키기 위하여 class-E 구조를 사용하여 soft-switching 특성을 활용하였다. Class-E 부하 회로의 DC-feed 인덕터는 유한한 값을 갖도록 하여 RF-choke을 사용하는 경우에 비해 동일한 전력과 공급 전압에 대해 필요로 하는 부하 저항의 크기를 증가시킴으로써 전력 효율을 더욱 증가시킬 수 있었다. 또한 common-gate switching 방법을 사용하여 기존의 switching 방법에 비해 허용되는 공급 전압의 크기를 두배 정도 증가시킬 수 있도록 하였다. 이러한 기법을 사용함으로써 900MHz의 주파수에서 공급 전압이 1.8V일 때 트랜지스터에 아무런 전압 stress를 가하지 않고 0.9W의 전력을 41%의 효율(power added efficiency, PAE)을 가지면서 50Ω 부하에 전달함을 확인하였다.

• 전자공학회논문지D
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• 제35D권5호
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• pp.1-10
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• 1998

A GaAs MMIC composed of VCO (voltage controlled oscillator) and mixer for PCS receiver has been developed using 1.mu.m ion implanted GaAs MESFET process. The VCO consists of a colpitts-type oscillator with a dielectric resonator and the circuit configuration of the mixer is a dual-gate type with an asymmetric combination of LO and RF FETs for the improvement of intermodulation characteristics. The common-source self-biasing is used in all circuits including a buffer amplifier and mixer, achieving a single power supply (3V) operation. The total power dissipation is 78mW. The VCO chip shows a phase noise of-99 dBc/Hz at 100KHz offset. The combined VCO/mixer chip shows a flat conversion gain of 2dB, the frequency-tuning factor of 80MHz/volts in the varacter bias ranging from 0.5V to 0.5V , and output IP3 of dBm at varactor bias of 0V. The fabricated chip size is 2.5mm X 1.4mm.

• 전자공학회논문지D
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• 제34D권10호
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• pp.14-23
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• 1997

An MMIC downconverting mixer for cellular phone application has been successfully developed using an MMIC process including $1 \mu\textrm{m}$ ion implanted gaAs MESFET and passive lumped elements consisting of spiral inductor, $Si_3N_4$ MIM capacitor and NiCr resistor. The configuration of the mixer presented in this paper is single-ended dual-gate FET mixer with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit is $1.4 mm \times 1.03 mm $ including all input matching circuits and a mixing circuit. The conversion gian and noise figure of the mixer at LO powr of 0 dBm are 5.5dB and 19dB, respectively. The two-tone IM3 characteristics are also measured, showing -60dBc at RF power of -30dBm. Allisolations between each port show better than 20dB.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.290-293
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• 2006

We designed the H-IPS that has similar aperture ratio to the AS-IPS with organic insulator. To improve the aperture ratio without organic insulator, we positioned the pixel electrode over the preceding gate on the base of the H-IPS structure, and minimized the width of pixel and common electrodes. Without the additional process, we could obtain the similar brightness with that of AS-IPS in 15inch SXGA+ Panel.