• Nuclear Engineering and Technology
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• 제56권4호
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• pp.1532-1537
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• 2024

Time-of-flight (TOF) PET detectors with fast-rise-time scintillators and fast-single photon time resolution silicon photomultiplier (SiPM) have been developed to improve the coincidence timing resolution (CTR) to sub-100 ps. The CTR can be further improved with an optimal bandwidth and minimized electronic noise in the readout circuit and this helps reduce the distortion of the fast signals generated from the TOF-PET detector. The purpose of this study was to develop an ultra-high frequency and fully-differential (UF-FD) readout circuit that minimizes distortion in the fast signals produced using TOF-PET detectors, and suppresses the impact of the electronic noise generated from the detector and front-end readout circuits. The proposed UF-FD readout circuit is composed of two differential amplifiers (time) and a current feedback operational amplifier (energy). The ultra-high frequency differential (7 GHz) amplifiers can reduce the common ground noise in the fully-differential mode and minimize the distortion in the fast signal. The CTR and energy resolution were measured to evaluate the performance of the UF-FD readout circuit. These results were compared with those obtained from a high-frequency and single ended readout circuit. The experiment results indicated that the UF-FD readout circuit proposed in this study could substantially improve the best achievable CTR of TOF-PET detectors.

• 대한의용생체공학회:의공학회지
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• 제20권2호
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• pp.205-212
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• 1999

수술실에서 수술도중 환자의 뇌파를 관찰하고자 할 경우에 전기수술기를 사용하게 되면 매우 높은 주파수와 큰 전압의 전기적 잡음이 발생하게 되며, 기존의 뇌파측정기는 이 잡음에 의해서 포화되어 뇌파 측정이 불가능하다. 본 연구에서는 고신뢰도의 뇌파 측정용 CSA 시스템을 구성하기 위하여 전기수술기의 간섭이 적은 양극 뇌파증폭기를 개발하고자 하였다. 개발된 양극 뇌파 증폭기는 balanced filter를 사용하여 전기수술기의 잡음이 뇌파 증폭기의 입력으로 들어가는 것을 줄이도록 하였으며, 전치증폭기의 전원과 신호를 접지와 분리하여 전기수술기에서 나온 전류가 뇌파 증폭기를 통해 접지로 흘러 들어가는 경로를 차단하였고, 높은 주파수에서도 CMRR 특성이 좋은 차동증폭기를 사용하여 고주파 성분의 공통 성분 잡음을 제거함으로써 전기수술기의 잡음을 상당히 줄일 수 있었다. 이와 같이 개발된 양극 뇌파증폭기는 고이득, 저잡음, 높은 CMRR, 고입력 임피던스, 낮은 열잡음 등의 특성을 가지므로 순수한 뇌파의 측정에 유용하며, 전기수술기를 사용할 경우에도 지속적으로 뇌파를 측정할 수 있는 고신뢰도의 CSA 시스템의 구현에 이용할 수 있다.

• 전기전자학회논문지
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• 제22권4호
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• pp.1006-1011
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• 2018

본 논문은 멀티비트 플라잉 커패시터의 전압제어를 이용한 3-레벨 벅 변환기를 제안한다. 기존의 3-레벨 벅 변환기는 플라잉 커패시터 전압을 제어하지 못하여 동작이 불안정하거나 플라잉 커패시터 전압을 제어하는 회로가 PWM방식에 적용되지 못하는 문제가 있었다. 또한 부하전류에 증가할 때 인덕터 전압에 오차가 발생하였다. 본 논문에서 제안하는 구조는 입력이 4개인 차동증폭기와 공통모드 피드백 회로를 이용하여 PWM모드에서 플라잉 커패시터 전압을 제어할 수 있다. 또한 3비트 플라잉 커패시터 전압 제어회로를 제안하여 부하전류에 따른 3-레벨 벅 변환기의 동작을 최적화할 수 있으며 슈미트 트리거 회로를 이용한 삼각파 생성 회로를 제안하였다. 제안하는 3-레벨 벅 변환기는 $0.18{\mu}m$ CMOS 공정으로 설계되었으며 2.7~3.6V의 공급 전압 범위와 0.7V~2.4V의 출력 전압 범위를 갖는다. 동작 주파수는 2MHz, 부하전류 범위는 30mA~500mA이며 출력 전압 리플은 최대 32.5mV로 측정되었다. 측정 결과 130mA의 부하전류에서 약 85%의 최대 전력변환 효율을 보인다.

• Earthquakes and Structures
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• 제2권1호
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• pp.65-88
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• 2011

A new method for the seismic design of plane steel moment resisting frames is developed. This method determines the design base shear of a plane steel frame through modal synthesis and spectrum analysis utilizing different values of the strength reduction (behavior) factor for the modes considered instead of a single common value of that factor for all these modes as it is the case with current seismic codes. The values of these modal strength reduction factors are derived with the aid of a) design equations that provide equivalent linear modal damping ratios for steel moment resisting frames as functions of period, allowable interstorey drift and damage levels and b) the damping reduction factor that modifies elastic acceleration spectra for high levels of damping. Thus, a new performance-based design method is established. The direct dependence of the modal strength reduction factor on desired interstorey drift and damage levels permits the control of deformations without their determination and secures that deformations will not exceed these levels. By means of certain seismic design examples presented herein, it is demonstrated that the use of different values for the strength reduction factor per mode instead of a single common value for all modes, leads to more accurate results in a more rational way than the code-based ones.

• Transactions on Electrical and Electronic Materials
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• 제17권2호
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• pp.57-68
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• 2016

In this study, we present the modern hybrid system based power generation for electric vehicle applications. We describe the hybrid structure of modified current source based DC - DC converters used to extract the maximum power from Photovoltaic (PV) and Fuel Cell system. Due to reduced dc-link capacitor requirement and higher reliability, the current source inverters (CSI) better compared to the voltage source based inverter. The novel control strategy includes Distributed Maximum Power Point Tracking (DMPPT) for photovoltaic (PV) and fuel cell power generation system. The proposed DC - DC converters have been analyzed in both buck and boost mode of operation under duty cycle 0.5>d, 0.5<d<1 and 0.5<d for capable electric vehicle applications. The proposed topology benefits include one common DC-AC inverter that interposes the generated power to supply the charge for the sharing of load in a system of hybrid supply with photovoltaic panels and fuel cell PEM. An improved control of Direct Torque and Flux Control (DTFC) based induction motor fed by current source converters for electric vehicle.In order to achieve better performance in terms of speed, power and miles per gallon for the expert, to accepting high regenerative braking current as well as persistent high dynamics driving performance is required. A simulation model for the hybrid power generation system based electric vehicle has been developed by using MATLAB/Simulink. The Direct Torque and Flux Control (DTFC) is planned using Xilinx ISE software tool in addition to a Modelsim 6.3 software tool that is used for simulation purposes. The FPGA based pulse generation is used to control the induction motor for electric vehicle applications. FPGA has been implemented, in order to verify the minimal error between the simulation results of MATLAB/Simulink and experimental results.

• 전기전자학회논문지
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• 제18권2호
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• pp.220-227
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• 2014

이 논문은 Dead-time을 갖는 톱니파 발생기를 이용하여 공통모드와 차동모드 피드백 루프를 구현한 Single-Inductor Dual-Output DC-DC Converter 설계에 관한 내용을 제시하고 있다. 제어회로에는 공통모드와 차동모드 피드백 루프를 Dead-time을 갖는 톱니파 발생기를 이용하여 동시에 사용하였다. 차동모드 피드백 루프에서 duty를 생성하기 위해서 전류 분배기 회로를 사용하여 공통모드 피드백에 의한 duty에 따라 dead-time이 유동적으로 변하는 톱니파형을 만드는 회로인 Dead-time을 갖는 톱니파 발생기를 추가하여 차동모드 피드백 회로를 구성하였다. 0.35um 공정을 사용하여 설계한 SIDO DC-DC Converter는 2.5V 입력으로부터 2.8V와 4.2V의 전압을 출력하며 최대 전력변환 효율은 95%이다. 출력간의 Cross regulation은 출력전류가 2배씩 증가할 경우 Boost1과 Boost2의 출력전압은 각각 3.57%, 4% 수준을 보이고 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 B
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• pp.1046-1048
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• 2002

The increase of triplen harmonics in three-phase four-wire systems leads to overloaded neutral conductor, common-mode noise problems, derating of transformers, and so on. Various compensator has been designed to prevent the problems associated with the triplen harmonics. But these can not protect distribution system effectively because the triplen harmonic source is distributed extensively and distribution system type is diverse. This paper explain the operation and installation of single phase active power filter to eliminate triplen harmonics and then it is verified by simulation.

• Journal of electromagnetic engineering and science
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• 제8권3호
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• pp.91-95
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• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

• Journal of Information Processing Systems
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• 제2권3호
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• pp.163-169
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• 2006

So far, little research has been conducted into developing a QAPM (Quality Assurance Process Model) for telecommunications applications on the basis of TMN. This is the first trial of the design of TMN-based QAPM on fault management with UML. A key attribute of the QAPM is that it can easily identify current deficiencies in a legacy system on the basis of TMN architecture. Using an empirical comparison with the legacy systems of a common carrier validates the QAPM as the framework for a future mode of the operation process. The results indicate that this paper can be used to build ERP(Enterprise Resource Planning) for a telecommunications fault management solution that is one of the network management application building blocks. The future work of this paper will involve applying the QAPM to build ERP for RTE (Real Time Enterprise) fault management solution and more research on ERP design will be necessary to accomplish software reuse.

• 전기학회논문지
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• 제58권8호
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• pp.1644-1650
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• 2009

An improved guarding circuit is applied to a transconductance driven-right-leg circuit to decrease common-mode current at measurement electrodes due to power-line interference. After showing conventional guarding circuit is instable due to gain-peaking when used with a transconductance DRL circuit, the effect of the proposed guarding circuit modified to suppress the gain-peaking by inserting a series resistor between shields and a shield driver was analyzed. It is shown that, besides stability, the proposed guarding circuit provides two other advantages: 1) The gain of the shield driver can be set to be unit nominally. 2) The loop gain of the transconductance DRL loop can be increased due to pole-zero canceling. The proposed circuit was implemented and the advantages were confirmed.