• KIPS Transactions on Computer and Communication Systems
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• v.9 no.1
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• pp.1-8
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• 2020

The thermal image device support image to detect infrared light from the object without light. It can use not only defence-related industry, but also civilian industry. This paper presents a new thermal image processing module using common image processor. The proposed module shows 10~20% performance improvement with normal mode and 50% performance improvement with sleep mode compared with the previously thermal image module based FPGA. and it guarantees high scalability according to modular system. In addition, the proposed module improves modulation and reuse, so it expect to have reduction of development period, low development cost. various application. In addition, it expect to have satisfaction of customer requirements, development design, development period, release date of product.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.2
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• pp.25-30
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• 2020

The thermal image system was widely used in the defence-related industry because of detect infrared light from the object without light. but, as the demand in the security system and automobile market increases, the civilian industry are expanding to the private sector. There are difficult to apply various requirement because of previous systems are based by FPGA, so it need new system that apply to various requirement. The proposed paper is thermal image processing system using common image processor. It has various requirement and scalable to support image input/output interface and device driver. If it is used to proposed system, it reduce development cost and period than previous system based FPGA. Because there has very high accessibility. In addition, it expect to have satisfaction of customer requirements, development cost, development period, release date of product.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.653-656
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• 2003

We have designed embedded web sewer system and ported Linux operating system version 2.4.5 at our system. And then We implemented to control and monitor widely separated hardware and implemented to monitor widely separated image using CMOS image sensor HV7131B. Web server is the Boa web server with General Public License. We designed for this system using of Intel's SA1110 ARM core base processor and connecting input and output device at GPIO port of SA1110. Device driver of General purpose I/O for Embedded Linux OS is designed. And then the application program controlling driver is implemented to use of common gate interface C language. User is available to control and monitor at client PC. This method have benefit to reduce the Expenditure of hardware design and development time against PC base system and have various and capacious application against firmware base system.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.62-70
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• 2007

In this paper, we design a mobile camera processor to support the MIPI CSI-2 and DPHY specification. The lane management sub-layer of CIS2 handles multi-lane configuration. Thus conceptually, the transmitter and receiver have each independent buffer on multi lanes. In the proposed architecture, the independent buffers are merged into a single common buffer. The single buffer architecture can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. For a key issue for the data synchronization problem, the synchronization start codes are added as the starting for image data. We design synchronization logic to synchronize the received clock and to generate the byte clock. We present the verification results under proposed test bench. And we show the waves of simulation and logic synthesis results of the designed processor.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.10a
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• pp.8-10
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• 2019

열화상 장비는 빛이 없는 암흑 상태에서도 물체에서 발산하는 적외선을 탐지하여 이를 영상으로 제공하는 장비이다. 이러한 장점으로 기존 활용되던 군사 분야와 더불어 자동차 및 감시시스템 등 다양한 민수 분야로 활용분야가 넓어지고 있다. 따라서 기존 방식인 FPGA 기반 열화상 이미지 모듈은 민수 시장의 다양한 요구사항과 환경을 반영하기에는 힘들 실정이다. 그에 따라 FPGA 기반 시스템의 단점을 보완하고 추가적인 요구사항을 만족하는 시스템의 필요성이 대두되었다. 본 논문에서는 상용 이미지 프로세서 기반 열화상 이미지 처리 모듈을 제안한다. 기존 FPGA 기반 열화상 이미지 처리 방식이 아닌 상용 이미지 프로세서 기반 구조 설계로 함으로써 다양한 영상 입·출력 인터페이스 수신 및 표준 영상 출력 포멧을 지원한다. 따라서 상용 프로세서 기반 열상 처리 모듈을 통한 시스템 개발 시 뛰어난 접근성으로 시스템 구축이 용이하고 다양한 요구사항 적용이 가능함에 따라 개발 기간 및 비용 단축, 다양한 응용에 사용이 가능할 것으로 예상한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.10a
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• pp.5-7
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• 2019

열화상 시스템은 물체로부터 발산되는 적외선을 영상화하여 물체를 탐지하는 장점으로 인해 군사 분야는 물론 현재 민수 분야(자동차, Security 시스템)에 활용분야가 넓어지고 있다. 기존에는 대부분 FPGA 기반으로 열화상 열상 모듈을 개발하였지만 민수 분야에 다양한 요구사항 및 범용성에 유연한 대처가 힘든 실정이다. 따라서 다양한 요구사항과 범용성을 만족하기 위한 시스템의 필요성이 대두되었다. 본 논문에서는 상용 이미지 프로세서를 이용한 열화상 영상 처리 시스템을 제안한다. 제안된 시스템은 기존 FPGA 기반 시스템이 아닌 상용 이미지 프로세서를 사용함으로써 범용 영상 입·출력 인터페이스 및 각종 디바이스를 지원함에 따라 다양한 요구사항과 범용성을 만족한다. 따라서 시스템이 구축이 되면 뛰어난 접근성으로 인하여 시스템 추가/변경 시 기존의 시스템에 비해 개발 비용 및 기간을 단축할 수 있으며 그로 인하여 다양한 고객 요구사항 만족, 개발 비용 및 시간 단축, 제품 출시일 등 다양한 이점을 얻을 것으로 예상한다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.13 no.2
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• pp.13-25
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• 2017

Recently, the high performance of tactical situation display console and tactical data links are used to integrate the operational situations in accordance with information age and NCW (Network Centric Warfare). The tendency to maximize the efficiency of task execution has been developed by sharing information and the state of the battle quickly through complex and diverse information exchange. Tactical data link is a communication system that shares the platform with core components of weapons systems and battlefield situation between the command and control systems to perform a Network Centric Warfare and provides a wide range of tactical data required for decision-making and implementation.It provides the tactical information such as tactical information such as operational information, the identification of the peer, and the target location in real time or near real time in the battlefield situation, and it is operated for the exchange of mass tactical information between the intellectuals by providing common situation recognition and cooperation with joint operations. In this study, still image management, audio file management, tactical screen recording and playback using the storage and playback, NITF (National Imagery Transmission Format) message received from the displayer integrates the tactical situation in three dimensions according to multiple data link operation to suggest ways to ensure data integrity between the data link processor during the entire operation time.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.102-110
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• 2009

In this paper, we propose an object detection method for real-time in infrared (IR) images and PowerPC (PPC) and H/W design based on field programmable gate array (FPGA). An open H/W architecture has the advantages, such as easy transplantation of HW and S/W, support of compatibility and scalability for specification of current and previous versions, common module design using standardized design, and convenience of management and maintenance. Proposed background modeling for an open H/W architecture design decreases size of search area to construct a sparse block template of search area in IR images. We also apply to compensate for motion compensation when image moves in previous and current frames of IR sensor. Separation method of background and objects apply to adaptive values through time analysis of pixel intensity. Method of clutter reduction to appear near separated objects applies to median filter. Methods of background modeling, object detection, median filter, labeling, merge in the design embedded system execute in PFC processor. Based on experimental results, proposed method showed real-time object detection through global motion compensation and background modeling in the proposed embedded system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.35-41
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• 2020

Fast Fourier transform (FFT) processors have been widely used in various application such as communications, image, and biomedical signal processing. Especially, high-performance and low-power FFT processing is indispensable in OFDM-based communication systems. This paper presents a novel radix-26 FFT algorithm with low computational complexity and high hardware efficiency. Applying a 7-dimensional index mapping, the twiddle factor is decomposed and then radix-26 FFT algorithm is derived. The proposed algorithm has a simple twiddle factor sequence and a small number of complex multiplications, which can reduce the memory size for storing the twiddle factor. When the coefficient of twiddle factor is small, complex constant multipliers can be used efficiently instead of complex multipliers. Complex constant multipliers can be designed more efficiently using canonic signed digit (CSD) and common subexpression elimination (CSE) algorithm. An efficient complex constant multiplier design method for the twiddle factor multiplication used in the proposed radix-26 algorithm is proposed applying CSD and CSE algorithm. To evaluate performance of the previous and the proposed methods, 256-point single-path delay feedback (SDF) FFT is designed and synthesized into FPGA. The proposed algorithm uses about 10% less hardware than the previous algorithm.